Memory controller, nonvolatile semiconductor memory device and memory system
According to one embodiment, a memory system includes a nonvolatile semiconductor memory and a memory controller. The memory controller has a first signal generation section that generates a first signal related with a read voltage used for read operation of the nonvolatile semiconductor memory, a second signal generation section that generates a second signal that specifies the temperature coefficient used for the correction for temperature of the read voltage, and a first interface section that outputs the first signal, the second signal and a read command. The nonvolatile semiconductor memory has a word line, a memory cell array includes memory cells connected to the word line, and a second interface section that receives the first signal, the second signal and the read command.
1. A memory system comprising a nonvolatile semiconductor memory and a memory controller controlling the nonvolatile semiconductor memory,
the memory controller comprising:
a first signal generation section configured to generate a first signal related with a read voltage used for read operation of the nonvolatile semiconductor memory;
a second signal generation section configured to generate a second signal for specifying a temperature coefficient used for temperature correction of the read voltage; and
a first interface section configured to output the first signal, the second signal, and a read command; and
the nonvolatile semiconductor memory comprising:
a word line;
a memory cell array comprising memory cells connected to the word line;
a second interface section configured to receive the first signal, the second signal, and the read command; and
a control section configured to generate the read voltage determined based on the first signal, to adjust the read voltage based on the temperature coefficient specified by the second signal, thereby generating the adjusted read voltage, to read data of the memory cells connected to the word line using the adjusted read voltage, and to output the read data through the second interface section to the memory controller,
wherein each of the memory cells is capable of storing n bits (n is a natural number of two or more), and
the memory controller is configured to:
set the first signal to a first value, and an i-th value (i is a natural number of two or more) in series, and set the second signal to a first value, and an i-th value in series, where the k-th value of the first signal corresponds to the k-th value of the second signal, the k-th value is one of the first to i-th values, and the temperature coefficient specified by the k-th value of the second signal is different from the temperature coefficient specified by the (k+1)-th value of the second signal when the read voltage specified by the k-th value of the first signal is provided in a first range different from the second range in which the read voltage specified by the (k+1)-th value of the first signal is provided, and
determine a 2 n threshold distribution of the memory cells based on the data obtained from the nonvolatile semiconductor memory by the first to i-th values of the first and second signals.
2. The memory system of claim 1 , wherein the memory controller further comprises a storage section configured to store a digital value corresponding to the read voltage for every read voltage and the first signal generation section generates the digital value as the first signal.
3. The memory system of claim 2 , wherein the storage section stores information specifying a temperature coefficient for every read voltage, and the second signal generation section generates the second signal based on the information specifying the temperature coefficient.
4. The memory system of claim 1 , wherein the control section outputs for every read voltage the read data through the second interface section to the memory controller.
5. The memory system of claim 1 , wherein the nonvolatile semiconductor memory is a multi-value memory having a 2 n threshold distribution (n is a natural number of two or more), and the temperature coefficient specified by the second signal is changed before and behind the read voltage corresponding to a mountain of the 2 n threshold distribution.
6. The memory system of claim 1 , wherein the nonvolatile semiconductor memory is a multi-value memory having a 2 n threshold distribution (n is a natural number of two or more), and the temperature coefficient specified by the second signal is changed before and behind the read voltage corresponding to a valley of the 2 n threshold distribution.
7. The memory system of claim 1 , wherein the second interface section receives an address along with the first signal, the second signal, and the read command, and the control section outputs through the second interface section to the memory controller the read data specified by the address.
8. A memory system comprising a nonvolatile semiconductor memory and a memory controller controlling the nonvolatile semiconductor memory,
the memory controller comprising:
a first signal generation section configured to generate a first signal specifying a read voltage used for read operation of the nonvolatile semiconductor memory and a temperature coefficient used for the correction for temperature of the read voltage;
a second signal generation section configured to generate a second signal for giving an instruction to subject the read voltage specified by the first signal to correction for temperature based on the temperature coefficient; and
a first interface section configured to output the first signal, the second signal, and a read command; and
the nonvolatile semiconductor memory comprising:
a word line;
a memory cell array comprising memory cells connected to the word line;
a second interface section configured to receive the first signal, the second signal, and the read command; and
a control section configured to generate the read voltage determined based on the first signal, to adjust the read voltage based on the temperature coefficient specified by the first signal, thereby generating the adjusted read voltage, to read data of the memory cells connected to the word line using the adjusted read voltage, and to output the read data through the second interface section to the memory controller,
wherein each of the memory cells is capable of storing n bits (n is a natural number of two or more), and
the memory controller is configured to:
set the first signal to a first value, . . . and an i-th value (i is a natural number of two or more) in series, and set the second signal to a first value, . . . and an i-th value in series, where the k-th value of the first signal corresponds to the k-th value of the second signal, the k-th value is one of the first to i-th values, and the temperature coefficient specified by the k-th value of the second signal is different from the temperature coefficient specified by the (k+1)-th value of the second signal when the read voltage specified by the k-th value of the first signal is provided in a first range different from a second range in which the read voltage specified by the (k+1)-th value of the first signal is provided, and
determine a 2 n threshold distribution of the memory cells based on the data obtained from the nonvolatile semiconductor memory by the first to i-th values of the first and second signals.
9. The memory system of claim 8 , wherein the nonvolatile semiconductor memory is a multi-value memory having a 2threshold distribution (n is a natural number of two or more), and the temperature coefficient specified by the second signal is changed before and behind the read voltage corresponding to a mountain of the 2 n threshold distribution.
10. The memory system of claim 8 , wherein the nonvolatile semiconductor memory is a multi-value memory having a 2 n threshold distribution (n is a natural number of two or more), and the temperature coefficient specified by the second signal is changed before and behind the read voltage corresponding to a valley of the 2 n threshold distribution.