Packet-processing scheduler, security context, authentication, packet header, air cipher subsystem
An electronic circuit ( 200 ) includes one or more programmable control-plane engines ( 410, 460 ) operable to process packet header information and form at least one command, one or more programmable data-plane engines ( 310, 320, 370 ) selectively operable for at least one of a plurality of cryptographic processes selectable in response to the at least one command, and a programmable host processor ( 100 ) coupled to such a data-plane engine ( 310 ) and such a control-plane engine ( 410 ). Other processors, circuits, devices and systems and processes for their operation and manufacture are disclosed.
1. A packet-processing electronic subsystem comprising:
a first data interface having an input for accepting first streaming data and having an output;
a second data interface having an input for accepting second streaming data and having an output;
a third data interface having an output for egress of third streaming data and having an input;
a fourth data interface having an output for egress of fourth streaming data and having an input, the first, second, third, and fourth data interfaces being separate from one another;
scheduler circuitry having inputs coupled to the outputs of the first and second interfaces, having outputs coupled to the inputs of the third, and fourth data interfaces, and including a packet memory, the scheduler circuitry having a security context cache interface, a packet header processor interface, an authentication interface, and an air cipher interface;
a security context cache coupled to the security context cache interface of the scheduler circuitry and including a cache controller and cache storage for a security context;
a packet header processor coupled to the packet header processor interface of the scheduler circuitry;
an authentication module coupled to the authentication interface of the scheduler circuitry; and
an air cipher module coupled to the air cipher interface of the scheduler circuitry, the air cipher module including processor and control circuitry.
2. The subsystem of claim 1 in which the first interface is a packet accelerator ingress Communication Processor Peripheral Interface (CPPI) streaming interface.
3. The subsystem of claim 1 in which the second interface is a code division multiple access (CDMA) ingress Communication Processor Perpheral Interface (CPPI) streaming interface.
4. The subsystem of claim 1 in which the third interface is a packet accelerator egress Communication Processor Peripheral Interface (CPPI) streaming interface.
5. The subsystem of claim 1 in which the fourth interface is a code division multiple access (CDMA) egress Communication Processor Peripheral Interface (CPPI) streaming interface.