Bonding process for a chip bonding to a thin film substrate
A bonding process for a chip bonded to a thin film substrate is disclosed. The thin film substrate has a thickness of about less than 500 um. Curvature occurs in the thin film substrate due to Coefficient of Temperature Expansion (CTE) mismatch for different materials between the dielectric material and the embedded circuitry, where cooling and heating is applied during fabrication. A temporary carrier is prepared for the thin film substrate to paste, a flatten process is applied by a roller thereon so that the curvature of the thin film substrate can be eliminated and facilitated for of chips to be bonded thereto.
1. A bonding process for a chip bonded to a thin film substrate, comprises:
preparing a thin film substrate which has curvature, the thin film substrate has a plurality of top pads and has a plurality of bottom pads; a density of the top pads is higher than a density of the bottom pads;
preparing a temporary carrier;
applied adhesive layer on a top surface of the temporary carrier;
pasting the thin film substrate on a top surface of the adhesive layer; and
flattening the thin film substrate.
2. A bonding process for a chip bonded to a thin film substrate as claimed in claim 1 , further comprising:
preparing a plurality of chips, each chip has a plurality of metal pillars on bottom and an underfill wrapping the metal pillars; and each chip has a plurality of bonding elements configured on bottom;
placing the plurality of chips onto the flattened thin film substrate; and
heating to bound the chips to the thin film substrate.
3. A bonding process for a chip bonded to a thin film substrate as claimed in claim 2 , further comprising:
molding the chips to form a package sheet;
releasing the package sheet from the temporary carrier;
forming solder mask on bottom of the thin film substrate and exposing a bottom surface of each bottom pad; and
singulating the package sheet to produce a plurality of package units.
4. A bonding process for a chip bonded to a thin film substrate as claimed in claim 1 , wherein the thin film substrate has a thickness less than 500 um.
5. A bonding process for a chip bonded to a thin film substrate as claimed in claim 1 , wherein the thin film substrate is a redistribution layer.
6. A bonding process for a chip bonded to a thin film substrate as claimed in claim 1 , wherein the chip is one of microchip and nanochip.
7. A bonding process for a chip bonded to a thin film substrate as claimed in claim 1 , wherein the bonding element of the chip is a metal pillar.
8. A bonding process for a chip bonded to a thin film substrate as claimed in claim 1 , further comprising:
preparing a plurality of chips, each chip has a plurality of bonding elements on bottom;
applying underfill material on top surface on the thin film substrate;
placing the plurality of chips onto the flattened thin film substrate;
heating to bound the chips to the thin film substrate.
9. A bonding process for a chip bonded to a thin film substrate as claimed in claim 8 , further comprising:
molding the chips to form a package sheet;
releasing the package sheet from the temporary carrier;
forming solder mask on bottom of the thin film substrate and exposing a bottom surface of each bottom pad;
singulating the package sheet to produce a plurality of package units.
10. A bonding process for a chip bonded to a thin film substrate as claimed in claim 8 , wherein the thin film substrate has a thickness less than 500 um.
11. A bonding process for a chip bonded to a thin film substrate as claimed in claim 8 , wherein the thin film substrate is a redistribution layer.
12. A bonding process for a chip bonded to a thin film substrate as claimed in claim 8 , wherein the chip is one of microchip and nanochip.
13. A bonding process for a Chip bonded to a thin film substrate as claimed in claim 8 , wherein the bonding element of the chip is a metal pillar.