Apparatuses and methods for asymmetric input/output interface for a memory
Apparatuses and methods for asymmetric input/output interfaces for memory are disclosed. An example apparatus may include a receiver and a transmitter. The receiver may be configured to receive first data signals having a first voltage swing and having a first slew rate. The transmitter may be configured to provide second data signals having a second voltage swing and having a second slew rate, wherein the first and second voltage swings are different, and wherein the first and second slew rates are different.
1. An apparatus, comprising:
a receiver configured to receive first data signals to be provided to a memory for a first memory command, the first data signals having a first voltage swing and having a first slew rate; and
a transmitter configured to provide second data signals to a memory controller for a second memory command, the second data signals having a second voltage swing and having a second slew rate,
wherein the first and second voltage swings are different,
wherein the first and second slew rates are different,
wherein the first voltage swing is greater than the second voltage swing, and
wherein the first slew rate is greater than the second slew rate.
2. The apparatus of claim 1 , wherein the first data signals are received over a bi-directional bus.
3. The apparatus of claim 2 , wherein the second data signals are provided over the bi-directional bus.
4. The apparatus of claim 1 , wherein the receiver is configured to receive the first data signals at an input/output (I/O) rate associated with the first slew rate, and wherein the transmitter is configured to provide the second data signals at the I/O rate.
5. A method, comprising:
receiving first data for an associated first memory command to be provided to a memory at a receiver from a memory controller, wherein the first data has a first voltage swing and a first slew rate; and
providing second data for an associated second memory command from a transmitter to the memory controller, wherein the second data has a second voltage swing and a second slew rate, and wherein the first voltage swing is greater than the second voltage swing, and wherein the first slew rate is greater than the second slew rate.
6. The method of claim 5 , further comprising receiving a clock signal at the memory from the memory controller.
7. The method of claim 6 , wherein the clock is embedded in the first data.
8. The method of claim 5 , wherein the memory is configured to detect smaller voltage swings than the memory controller.
9. The method of claim 5 , further comprising providing a clock to the memory from the memory controller.
10. An apparatus, comprising:
an asymmetric transceiver configured to receive first data signals to be provided to a memory for a memory command, the first data signals having a first voltage swing and a first slew rate, and further configured to provide second data signals to a memory controller for a second memory command, the second data signals having a second voltage swing and a second slew rate, wherein the first voltage swing is larger than the second voltage swing, and wherein the first slew rate is faster than the second slew rate.
11. The apparatus of claim 10 , wherein the asymmetric transceiver is configured to receive the first data signals at an input/output (I/O) rate associated with the first slew rate, and wherein the asymmetric transceiver is configured to provide the second data signals at the I/O rate.
12. The apparatus of claim 10 , wherein the asymmetric transceiver comprises a receiver configured to receive the first data signals associated with a write command and a transmitter configured to provide the second data signals associated with a read command.
13. The apparatus of claim 12 , wherein the receiver comprises a sense amplifier and a latch and the transmitter comprises a plurality of series coupled transistors.
14. The apparatus of claim 10 , further comprising an input/output controller coupled to the asymmetric transceiver and configured to provide control signals for enabling the transceiver.
15. The apparatus of claim 10 , wherein the memory comprises a dynamic random access memory.
16. A system, comprising:
a first device configured to output a first signal to be provided to a memory for a first memory command, the first signal including a first voltage swing and a first slew rate; and
a second device configured to output a second signal to a controller for a second memory command, the second memory command responsive to the first memory command, the second signal including a second voltage swing and a second slew rate, wherein the first voltage swing and the second voltage swing are different, wherein the first voltage swing is larger than the second voltage swing, and wherein the first slew rate is faster than the second slew rate.
17. The system of claim 16 , wherein the second device includes a transmitter to output the second signal, wherein the transmitter is configured to be coupled between a voltage line and the common voltage line, wherein the voltage line and the common voltage line are different in a voltage.
18. The system of claim 16 , further comprising a command address bus configured to transfer command and address signals to the memory from the controller, and a clock bus configured to transfer clock signal to the memory from the controller.
19. The system of claim 16 , wherein the controller outputs the first signal as write data responsive to the first memory command being a write command and the memory outputs the second signal responsive to second memory command being a read command from the controller.