Circuits and techniques including cascaded LDO regulation
A regulator circuit can include a cascaded topology, comprising a first integrated low-dropout (LDO) regulator circuit having a supply node, the first integrated LDO regulator circuit configured to provide a first loop bandwidth and configured to provide a regulated first output voltage to an intermediate node using energy provided by the supply node, and a second integrated LDO regulator circuit having an input coupled to the intermediate node, the second LDO regulator circuit configured to provide a second loop bandwidth and configured to provide a regulated second output voltage to an output node, where the second loop bandwidth is narrower than the first loop bandwidth. The regulator circuit need not require an external capacitor. The regulator circuit can be used to provide one or more of enhanced power supply rejection and noise performance.
1. A regulator circuit having a cascaded topology, comprising:
a first integrated low-dropout (LDO) regulator circuit having a supply node, the first integrated LDO regulator circuit configured to provide a first loop bandwidth and, using a loop gain much greater in magnitude than unity in a specified frequency range from about 10 kilohertz (kHz) to about 10 megahertz (MHz), configured to provide a regulated first output voltage to an intermediate node using energy provided by the supply node; and
a second integrated LDO regulator circuit having an input coupled to the intermediate node, the second LDO regulator circuit configured to provide a different second loop bandwidth and, using a loop gain much less in magnitude than unity in the specified frequency range from about 10 kilohertz (kHz) to about 10 megahertz (MHz), configured to provide a regulated second output voltage to an output node.
2. The regulator circuit of claim 1 , wherein the first and second integrated LDO regulator circuits each comprise an error amplifier coupled to a pass transistor.
3. The regulator circuit of claim 2 , wherein the pass transistor of the first integrated LDO regulator includes a first conductivity type; and
wherein the pass transistor of the second integrated LDO regulator circuit includes an opposite second conductivity type.
4. The regulator circuit of claim 3 , wherein the pass transistor of the first integrated LDO regulator includes a PMOS device; and
wherein the pass transistor of the second integrated LDO regulator circuit includes an NMOS device.
5. The regulator circuit of claim 3 , wherein the NMOS device comprises a native device.
6. The regulator circuit of claim 1 , wherein the first integrated LDO regulator circuit comprises:
a folded cascode stage; and
a buffer stage coupled between the folded cascode stage and the integrated pass transistor.
7. The regulator circuit of claim 6 , comprising a series RC network configured to provide a zero near a frequency corresponding to a unity gain bandwidth of the first integrated LDO regulator circuit.
8. The regulator circuit of claim 6 , wherein the folded cascode stage comprises at least one compensating capacitor coupled to a current buffer, the current buffer comprising a portion of the folded cascode stage.
9. The regulator circuit of claim 1 , wherein the second integrated LDO comprises a differential transconductance stage; and
a source follower stage with transconductance, the source follower stage coupled between the differential transconductance stage and the pass transistor.
10. The regulator circuit of claim 1 , wherein the output of the second integrated LDO regulator circuit is coupled to an integrated decoupling capacitor.
11. The regulator circuit of claim 1 , wherein the first and second LDO regulator circuits are coupled to a voltage reference; and
wherein a device noise specification and power supply rejection specification of the voltage reference are relaxed as compared to a regulator circuit configuration lacking a cascaded configuration of the first and second LDO regulator circuits, lacking a loop gain of the first LDO regulator circuit having a magnitude much greater than unity in the specified frequency range, and lacking a loop gain of the second LDO regulator circuit having a magnitude much less in magnitude than unity in the specified frequency range.
12. The regulator circuit of claim 1 , wherein the first and second LDO regulator circuits are configured to provide a specified PSRR and a specified output noise voltage density when driving a load circuit comprising one or more of a phase-locked-loop, a voltage-controlled oscillator, a low-noise amplifier, or a power amplifier without requiring a discrete capacitor coupled to the output node external to an integrated circuit comprising the first and second integrated LDO regulators.
13. A regulator circuit having a cascaded topology, comprising:
a first integrated low-dropout (LDO) regulator circuit having a supply node, the first integrated LDO regulator circuit configured to provide a first loop bandwidth and, using a loop gain much greater in magnitude than unity in a specified frequency range from about 10 kilohertz (kHz) to about 10 megahertz (MHz), configured to provide a regulated first output voltage to an intermediate node using energy provided by the supply node; and
a second integrated LDO regulator circuit having an input coupled to the intermediate node, the second LDO regulator circuit configured to provide a second loop bandwidth and, using a loop gain much less in magnitude than unity in the specified frequency range from about 10 kilohertz (kHz) to about 10 megahertz (MHz), configured to provide a regulated second output voltage to an output node;
wherein the second loop bandwidth is narrower than the first loop bandwidth; and
wherein the first and second LDO regulator circuits are configured to provide a specified power supply rejection ratio (PSRR) and a specified output noise voltage density without requiring a discrete capacitor coupled to the output node external to an integrated circuit comprising the first and second integrated LDO regulators;
wherein the pass transistor of the first integrated LDO regulator includes a PMOS device; and
wherein the pass transistor of the second integrated LDO regulator circuit includes an NMOS device.
14. The regulator circuit of claim 13 , wherein the NMOS device comprises a native device.
15. A method, comprising:
coupling a first integrated low-dropout (LDO) regulator circuit to a source to provide a regulated first output voltage to an intermediate node using a loop gain much greater in magnitude than unity in a specified frequency range; and
coupling a second integrated LDO regulator circuit to the intermediate node, including powering the second integrated LDO regulator circuit using the intermediate node, to provide a regulated second output voltage to an output node using a loop gain much less in magnitude than unity in the specified frequency range.
16. The method of claim 15 , comprising coupling the output node to a load circuit without requiring an external capacitor.
17. The method of claim 16 , wherein the load circuit comprises one or more of a phase-locked-loop, a voltage-controlled oscillator, a low-noise amplifier, or a power amplifier.
18. The method of claim 15 , wherein the first and second LDO regulator circuits are configured to provide a specified power supply rejection ratio (PSRR) and a specified output noise voltage density without requiring a discrete capacitor coupled to the output node external to an integrated circuit comprising the first and second integrated LDO regulators.
19. The method of claim 15 , wherein the specified frequency range extends from about 10 kilohertz (kHz) to about 10 megahertz (MHz).