Apparatuses and methods for controlling refresh operations
View Patent ↗An apparatus includes a first word line, a second word line and a control. The second word line is contiguous to the first word line. The control circuit includes a first defective address storing circuit and a first detection circuit. The first defective address storing circuit stores first enable information along with first defective address. The first enable information indicates whether or not the second word line is functional. The first detection circuit provides a first signal when the first word line is accessed. The first signal indicates whether or not the second word line is functional. The control circuit activates the second word line when the first signal indicates that the second word line is functional and does not activate the second word line when the first signal indicates that the second word line is not functional.
1. An apparatus comprising:
a first word line and a second word line being contiguous to the first word line;
a control circuit comprises:
a first defective address storing circuit configured to store first enable information along with first defective address information, the first enable infoiniation indicates whether the second word line is functional or the second word line is not functional, and
a first detection circuit configured to provide a first signal based, at least in part, on the first enable information when the first word line is accessed, the first signal indicates whether the second word line is functional or the second word line is not functional; and
wherein the control circuit is configured to activate the second word line for a target-row refresh operation when the first signal indicates that the second word line is functional and not to activate the second word line and instead activate another word line for the target-row refresh operation when the first signal indicates that the second word line is not functional.
2. The apparatus as claimed in claim 1 , wherein the first word line is a redundant word line and the second word line is a redundant word line.
3. The apparatus as claimed in claim 2 , further comprising a third word line that is a normal word line, and wherein the first defective address information designates the third word line.
4. The apparatus as claimed in claim 3 , further comprising a fourth word line that is a normal word line, and wherein the control circuit further comprises a second defective address storing circuit configured to store second enable information along with second defective address information, the second enable information indicates whether the first word line is functional or the first word line is not functional, the second defective address information designates the fourth word line, the control circuit is configured to selectively activate the second word line for the target-row refresh operation responsive, at least in part, to the second enable information.
5. The apparatus as claimed in claim 1 , wherein the first word line is a normal word line and the second word line is a redundant word line.
6. The apparatus as claimed in claim 5 , wherein the control circuit further comprises a second detection circuit configured to detect whether or not access address information externally supplied indicates the first word line and provide a second signal, and the first detection circuit is configured to provide the first signal responsive, at least in part, to the second signal.
7. The apparatus as claimed in claim 1 , further comprising a third word line being contiguous to the first word line in an opposite side of the second word line, and wherein the control circuit is configured to activate the second word line for the target-row refresh operation when the first signal indicates the second word line is functional and instead activate the third word line for the target-row refresh operation when the first signal indicates the second word line is not functional.
8. The apparatus as claimed in claim 1 , wherein the first defective address storing circuit includes a plurality of fuse elements.
9. The apparatus as claimed in claim 1 , wherein the first defective address storing circuit includes a plurality of anti-fuse elements.