Comparison operations on logical representations of values in memory
One example of the present disclosure includes performing a comparison operation in memory using a logical representation of a first value stored in a first portion of a number of memory cells coupled to a sense line of a memory array and a logical representation of a second value stored in a second portion of the number of memory cells coupled to the sense line of the memory array. The comparison operation compares the first value to the second value, and the method can include storing a logical representation of a result of the comparison operation in a third portion of the number of memory cells coupled to the sense line of the memory array.
1. A method for comparing values comprising:
performing a comparison operation in memory using a logical representation of a first value stored in a first portion of a number of memory cells coupled to a sense line of a memory array and a logical representation of a second value stored in a second portion of the number of memory cells coupled to the sense line of the memory array;
wherein the comparison operation compares the first value to the second value;
wherein performing the comparison operation comprises performing a plurality of logical operations, wherein performing at least one of the plurality of logical operations comprises sequentially activating a single select line at a time; and
storing a logical representation of a result of the comparison operation in a third portion of the number of memory cells coupled to the sense line of the memory array.
2. The method of claim 1 , further comprising storing the logical representation of the first value as a bit-vector in the first portion of the number of memory cells coupled to the sense line wherein each memory cell in the first portion of the number of memory cells stores a respective bit from the bit-vector.
3. The method of claim 1 , further comprising storing the logical representation of the second value as a bit-vector in the second portion of the number of memory cells coupled to the sense line wherein each memory cell in the second portion of the number of memory cells stores a respective bit from the bit-vector.
4. The method of claim 1 , wherein storing the logical representation of the result of the comparison operation comprises:
storing the logical representation of the result of the comparison operation as a bit-vector in the third portion of the number of memory cells coupled to the sense line wherein each memory cell in the third portion of the number of memory cells stores a respective bit from the bit-vector.
5. The method of claim 4 , wherein the bit-vector in the third portion of the number of memory cells comprises at least a two bit-vector.
6. The method of claim 1 , wherein the comparison operation determines whether the first value is different than the second value.
7. The method of claim 6 , wherein the comparison operation determines one of:
whether the second value is greater than the first value; and
whether the first value is greater than the second value.
8. The method of claim 1 , wherein the comparison operation determines whether the first value is equal to the second value.
9. The method of claim 1 , wherein the comparison operation includes clearing a compute component and the third number of memory cells that store the logical representation of the result of the comparison operation.
10. The method of claim 1 , wherein the comparison operation includes:
determining whether bits that are stored in the first portion of the number of memory cells are equal to bits that are stored in the second portion of the number of memory cells;
wherein corresponding bits from the first portion of the number of memory cells are compared to corresponding bits from the second portion of the number of memory cells.
11. The method of claim 10 , wherein determining whether bits that are stored in the first portion of the number of memory cells are equal to bits that are stored in the second portion of the number of memory cells comprises:
determining whether bits with a first index from the first value and the second value are equal before determining whether bits with a second index are equal;
wherein the first index is a more significant index than a second index.
12. A method for performing a number of comparison operations comprising:
comparing a number of first values stored in a number of first portions of memory cells coupled to a number of sense lines of a memory array to a number of second values stored in a number of second portions of the memory cells coupled to the number of sense lines of the memory array using a number of compute components that are coupled to the number of sense lines of the memory array;
wherein comparing the number of first values to a number of second values comprises performing a plurality of logical operations, wherein at least one of the plurality of logical operations is performed without activating more than one select line concurrently;
storing a number of results of a number of comparison operations in a number of third portions of the memory cells coupled to the number of sense lines of the memory array; and
wherein each of the number of comparison operations use a same number of computations to perform each of the number of comparison operations.
13. The method of claim 12 , wherein each of the number of first portions of the memory cells is coupled to a different sense line of the number of sense lines.
14. The method of claim 13 , wherein each of the number of second portions of the memory cells is coupled to a different sense line of the number of sense lines.
15. The method of claim 14 , wherein each of the number of comparison operations comprises a respective first value from the number of first values being compared to a respective second value from the number of second values wherein the first value and the second value of a respective comparison operation of the number of comparison operations are stored in memory cells coupled to the same sense line of the number of sense lines.
16. The method of claim 15 , wherein comparing the number of first values to the number of second values further comprises:
performing a first number of exclusive disjunction (XOR) operations using a number of next most significant bits from each of the number of first values and a corresponding number of next most significant bits stored in the number of second values as input.
17. The method of claim 16 , wherein comparing the number of first values to the number of second values further comprises:
performing a second number of XOR operations using a number of results of the first number of XOR operations and a number of bits stored in a number of fourth portions of the memory cells coupled to the number of sense lines of the memory array as input;
wherein the number of fourth portions of the memory cells are used to store a logical representation of a number of first temporary values that identify whether it has been determined that the number of first values are not equal to the number of second values.
18. The method of claim 17 , wherein comparing the number of first values to the number of second values further comprises:
storing a number of results of the second number of XOR operations in a number of fifth portions of the memory cells coupled to the number of sense lines of the memory array;
wherein the number of fifth portions of the memory cells are used to store a logical representation of a number of second temporary values that identify whether the number of next most significant bits from each of the number of first values are not equal to the corresponding number of next most significant bits from each of the number of second values.
19. The method of claim 18 , wherein comparing the number of first values to the number of second values further comprises:
performing a first number of disjunction (OR) operations using a number of bits stored in the number of fifth portions of the memory cells coupled to the number of sense lines of the memory array and the number of bits stored in the number of fourth portions of the memory cells coupled to the number of sense lines of the memory array as input;
storing a number of results of the first number of OR operations in the number of fourth portions of the memory cells to update the number of first temporary values.
20. The method of claim 19 , wherein comparing the number of first values to the number of second values further comprises:
performing a first number of conjunction (AND) operations using the number of next most significant bits from the number of first values and the bits stored in the number of fifth portions of the memory cells as input to determine whether the number of first values are greater than the number of second values.
21. The method of claim 20 , wherein comparing the number of first values to the number of second values further comprises:
performing a second number of OR operations using a number of results of the first number of AND operations and a number of bits stored in the number of third portions of the memory cells as input; and
storing a number of results of the second number of OR operations in the number of third portions of the memory cells.
22. The method of claim 21 , wherein comparing the number of first values to the number of second values further comprises:
performing a second number of AND operations using the number of next most significant bits from the number of second values and the bits stored in the number of fifth portions of the memory cells as input to determine whether the number of second values are greater than the number of first values.
23. The method of claim 22 , wherein comparing the number of first values to the number of second values further comprises:
performing a third number of OR operations using a number of results of the second number of AND operations and another number of bits stored in the number of third portions of the memory cells; and
storing a number of results of the third number of OR operations in the number of third portions of the memory cells.
24. The method of claim 23 , wherein comparing the number of first values to the number of second values further comprises:
if storing the number of results of the third number of OR operations in the number of third portions of the memory cells comprises the number of compute components latching a bit that indicates that all of the number of first values are equal to the number of second values:
ending the execution of the number of comparison operations.