Chip and an electronic device
A method for processing a carrier accordance with various embodiments may include: forming a structure over the carrier, the structure including at least two adjacent structure elements arranged at a first distance between the same; depositing a spacer layer over the structure, wherein the spacer layer may be deposited having a thickness greater than half of the first distance, wherein the spacer layer may include electrically conductive spacer material; removing a portion of the spacer layer, wherein spacer material of the spacer layer may remain in a region between the at least two adjacent structure elements; and electrically contacting the remaining spacer material.
1. An electronic device comprising:
a structure over a carrier, the structure comprising two adjacent structure elements respectively formed in a U-shape so that a contact region is provided between the same;
a patterned spacer layer that provides electrically conductive spacer material in the contact region between the at least two adjacent structure elements, wherein the patterned spacer layer electrically contacts the two adjacent structure elements; and
an electrical contact disposed over the patterned spacer layer to electrically contact the patterned spacer layer,
wherein the electrically conductive spacer material is in physical contact with a sidewall of each of the two adjacent structure elements and wherein a surface of each of the two adjacent structure elements is at least partially free of the electrically conductive spacer material, and
wherein the electrically conductive spacer material at the sidewall of each of the two adjacent structure elements provides a control line of a metal-oxide-semiconductor field-effect transistor.
2. The electronic device of claim 1 ,
wherein each of the two adjacent structure elements is at least a part of a metal-oxide-semiconductor field-effect transistor.
3. The electronic device of claim 2 ,
wherein each of the two adjacent structure elements is a part of a gate of a metal-oxide-semiconductor field-effect transistor.
4. The electronic device of claim 3 ,
wherein the each of the two adjacent structure elements comprises a floating gate of a metal-oxide-semiconductor field-effect transistor.
5. The electronic device of claim 1 ,
wherein each of the two adjacent structure elements comprises at least one of a floating gate and a control gate of a floating gate metal-oxide-semiconductor field-effect transistor.
6. The electronic device of claim 1 ,
wherein the patterned spacer layer comprises polycrystalline silicon.
7. The electronic device of claim 1 ,
wherein the patterned spacer layer is electrically contacted between the two adjacent structure elements by the electrical contact.
8. A chip comprising:
a structure disposed over a substrate, wherein the structure comprises at least one structure element, wherein each of the at least one structure element comprises at least two adjacent sidewalls facing each other so that a contact region is provided between the at least two adjacent sidewalls;
a patterned spacer layer that provides electrically conductive spacer material in the contact region between the at least two adjacent sidewalls, wherein the patterned spacer layer electrically contacts the at least one structure element; and
an electrical contact disposed over the patterned spacer layer to electrically contact the patterned spacer layer,
wherein the patterned spacer layer is electrically contacted between the at least two adjacent sidewalls of each of the at least one structure element by the electrical contact,
wherein the electrically conductive spacer material is in contact with the at least two adjacent sidewalls of each of the at least one structure element and wherein a surface of each of the at least one structure element is at least partially free of the electrically conductive spacer material, and
wherein the electrically conductive spacer material at the at least two adjacent sidewalls of each of the at least one structure element provides a control line of a metal-oxide-semiconductor field-effect transistor.
9. The chip of claim 8 ,
wherein each of the at least one structure element comprises at least one of a floating gate and a control gate of a floating gate metal-oxide-semiconductor field-effect transistor.
10. The chip of claim 8 ,
wherein the patterned spacer layer comprises polycrystalline silicon.
11. A chip comprising:
a structure disposed over a substrate, wherein the structure comprises two structure elements, wherein each of the two structure elements comprises at least two adjacent sidewalls facing each other so that each of the two structure elements further comprises a third sidewall, wherein the two third sidewalls of the two structure elements are facing each other so that a contact region is provided between the two third sidewalls of the two structure elements;
a patterned spacer layer that provides electrically conductive spacer material in the contact region between the two third sidewalls of the two structure elements, wherein the patterned spacer layer electrically contacts the two structure elements; and
an electrical contact disposed over the patterned spacer layer to electrically contact the patterned spacer layer,
wherein each of the two structure elements comprises at least one of a floating gate and a control gate of a floating gate metal-oxide-semiconductor field-effect transistor, and
wherein the electrically conductive spacer material between the two third sidewalls of the two structure elements provides a single control line for the two floating gate metal-oxide-semiconductor field-effect transistors.
12. The chip of claim 11 ,
wherein the patterned spacer layer comprises polycrystalline silicon.
13. The chip of claim 11 ,
wherein the electrically conductive spacer material is in physical contact with the two third sidewalls of the two structure elements.
14. A chip comprising:
a structure disposed over a substrate, wherein the structure comprises at least one structure element, wherein each of the at least one structure element comprises at least two adjacent sidewalls facing each other so that a contact region is provided between the at least two adjacent sidewalls;
a patterned spacer layer that provides electrically conductive spacer material in the contact region between the at least two adjacent sidewalls, wherein the patterned spacer layer electrically contacts the at least one structure element; and
an electrical contact disposed over the patterned spacer layer to electrically contact the patterned spacer layer,
wherein the electrically conductive spacer material is in contact with the at least two adjacent sidewalls of each of the at least one structure element and wherein a surface of each of the at least one structure element is at least partially free of the electrically conductive spacer material, and
wherein the electrically conductive spacer material at the at least two adjacent sidewalls of each of the at least one structure element provides a control line of a metal-oxide-semiconductor field-effect transistor.
15. The chip of claim 14 ,
wherein each of the at least one structure element comprises at least one of a floating gate and a control gate of a floating gate metal-oxide-semiconductor field-effect transistor.
16. The chip of claim 14 ,
wherein the patterned spacer layer comprises polycrystalline silicon.