IP Library Patent Application 14721152
Patent Application
App. No. 14/721,152

DEBUG TRIGGER INTERFACE FOR NON-DEBUG DOMAIN SYSTEM RESET

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Quick Facts
Patent No.
US None
App. No.
14/721,152
Abstract

A system, such as a system-on-chip, has a non-debug domain and a debug domain. The debug domain has a debug framework that enables a debugger driven, non-debug domain system reset. The system includes a reset control unit, and a debug trigger mechanism that includes a debug trigger interface (DTI) connected to the reset control unit. The DTI is configured to trigger the reset control unit to reset the non-debug domain. The DTI may further be configured to monitor a status of the non-debug domain system reset.

Claims (27)

1 . A system-on-chip comprising:

a reset control unit configured to reset a non-debug domain; and

a debug domain that includes a debug trigger interface connected to the reset control unit, wherein the debug trigger interface is configured to trigger the reset control unit to reset the non-debug domain.

2 . The system-on-chip of claim 1 , wherein the debug trigger interface has a trigger output connected to a non-debug domain system reset request of the reset control unit.

3 . The system-on-chip of claim 2 , wherein the trigger output is connected to the non-debug domain system reset request via an inverter.

4 . The system-on-chip of claim 1 , wherein the debug trigger interface is further configured to monitor a status of the non-debug domain system reset.

5 . The system-on-chip of claim 4 , wherein the debug trigger interface has a trigger input connected to a non-debug domain system reset status of the reset control unit.

6 . The system-on-chip of claim 5 , wherein the trigger input is connected to the non-debug domain system reset status via an inverter.

7 . The system-on-chip of claim 1 , wherein the debug trigger interface includes an application trigger register configured to cause the debug trigger interface to issue a non-debug domain system reset request to the reset control unit.

8 . The system-on-chip of claim 1 , wherein the debug trigger interface includes an application trigger in status register configured to indicate a status of the non-debug domain system reset received from the reset control unit.

9 . The system-on-chip of claim 1 , wherein the debug trigger interface includes an application pulse register configured to cause the debug trigger interface to issue a non-debug domain system reset request to the reset control unit for a defined time.

10 . A method for enabling a non-debug domain system reset of a system, wherein the system includes a debug trigger interface connected to a reset control unit, the method comprising:

issuing a non-debug domain system reset request from the debug trigger interface to the reset control unit, such that the debug trigger interface triggers the reset control unit to reset a non-debug domain of the system.

11 . The method of claim 10 , wherein the non-debug domain system reset request is issued from a trigger output of the debug trigger interface connected to a non-debug domain system reset request of the reset control unit.

12 . The method of claim 11 , further comprising inverting the non-debug domain system reset request issued to the reset control unit.

13 . The method of claim 10 , wherein the debug trigger interface includes an application trigger register, and the debug trigger interface issues the non-debug domain system based on a state of the application trigger register.

14 . The method of claim 10 , further comprising monitoring, by the debug trigger interface, a non-debug domain system reset status.

15 . The method of claim 14 , wherein the monitoring includes observing a status of a trigger input of the debug trigger interface connected to a non-debug domain system reset status of the reset control unit.

16 . The method of claim 15 , further comprising inverting a non-debug domain system reset status signal received by the trigger input from the reset control unit.

17 . The method of claim 14 , wherein the debug trigger interface includes an application trigger in status register, and the debug trigger interface sets a state of the application trigger in status register based on a non-debug domain system reset status received from the reset control unit.

18 . A non-transitory media encoded with logic that includes code for execution and, when executed by a processor, operable to perform operations comprising:

defining a non-debug domain system reset request channel between a debug trigger interface and a reset control unit; and

configuring the debug trigger interface to trigger the reset control unit to reset the non-debug domain.

19 . The non-transitory media of claim 18 , the operations further comprising monitoring a status of the non-debug domain system reset.

20 . The non-transitory media of claim 19 , the operations further comprising:

setting a state of an application trigger register to cause the debug trigger interface to issue a non-debug domain system reset request to the reset control unit; and

polling a state of an application trigger in status register, wherein the state of the application trigger in register is based on a non-debug domain system reset status received from the reset control unit.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 25, 2022
From: ANALOG DEVICES GLOBAL UNLIMITED COMPANY
To: ANALOG DEVICES INTERNATIONAL UNLIMITED COMPANY
Reel/Frame 059104/0171 →
CHANGE OF NAME Recorded Feb 24, 2022
From: ANALOG DEVICES GLOBAL
To: ANALOG DEVICES GLOBAL UNLIMITED COMPANY
Reel/Frame 059094/0579 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 28, 2015
From: GRAFTON, RICHARD F.; WENTWORTH, CHAD R.; NAGARAJA, YASHWANTH
To: ANALOG DEVICES GLOBAL
Reel/Frame 035737/0339 →