Encoder by-pass with scrambler
A first physical location is read to obtain read data. Error correction decoding is performed on the read data to obtain error-corrected data where the error-corrected data includes first error-corrected metadata. Error correction encoding is performed on a first random sequence combined with a second random sequence, concatenated with second metadata. Error correction encoding is also performed on a sequence of zeros concatenated with the first error-corrected metadata to obtain second encoded data. The error-corrected data, the first encoded data, and the second encoded data are summed to obtain migrated data, which is stored at a second physical location.
1. A system, comprising:
a storage; and
a host issuing instructions to a storage interface for communicating with the storage, wherein
the storage interface including an error correction decoder, an error correction encoder, and an adder, is configured to:
read a first physical location in the storage to obtain read data; and
store migrated data at a second physical location in the storage;
the error correction decoder is configured to:
perform error correction decoding on the read data in order to obtain error-corrected data, wherein the error-corrected data includes first error-corrected metadata;
the error correction encoder is configured to:
perform error correction encoding on (1) a first random sequence combined with a second random sequence, concatenated with (2) second metadata to obtain first encoded data; and
perform error correction encoding on a sequence of zeros concatenated with the first error-corrected metadata in order to obtain second encoded data; and
the adder is configured to sum (1) the error-corrected data, (2) the first encoded data, and (3) the second encoded data in order to obtain the migrated data.
2. The system of claim 1 , wherein the system includes a semiconductor device, including one or more of the following: an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA).
3. The system of claim 1 , wherein error correction encoding is performed on (1) the first random sequence combined with the second random sequence, concatenated with (2) the second metadata while error correction decoding is performed on the read data.
4. The system of claim 1 , wherein the storage includes solid state storage.
5. The system of claim 1 , wherein the error correction encoder and the error correction decoder are configured to use one or more of the following codes: a BCH code or a low-density parity-check (LDPC) code.
6. A method, comprising:
reading a first physical location in storage to obtain read data;
using an error correction decoder to perform error correction decoding on the read data in order to obtain error-corrected data, wherein the error-corrected data includes first error-corrected metadata;
using an error correction encoder to:
perform error correction encoding on (1) a first random sequence combined with a second random sequence, concatenated with (2) second metadata to obtain first encoded data; and
perform error correction encoding on a sequence of zeros concatenated with the first error-corrected metadata in order to obtain second encoded data;
summing (1) the error-corrected data, (2) the first encoded data, and (3) the second encoded data in order to obtain migrated data; and
storing the migrated data at a second physical location in the storage.
7. The method of claim 6 , wherein the method is performed by a semiconductor device, including one or more of the following: an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA).
8. The method of claim 6 , wherein error correction encoding is performed on (1) the first random sequence combined with the second random sequence, concatenated with (2) the second metadata while error correction decoding is performed on the read data.
9. The method of claim 6 , wherein the storage includes solid state storage.
10. The method of claim 6 , wherein performing error correction encoding and performing error correction decoding include using one or more of the following codes: a BCH code or a low-density parity-check (LDPC) code.
11. A computer program product, the computer program product being embodied in a non-transitory computer readable storage medium and comprising computer instructions, the computer instructions are executed by a processor and suitable for:
reading a first physical location in storage to obtain read data;
performing error correction decoding on the read data in order to obtain error-corrected data, wherein the error-corrected data includes first error-corrected metadata;
performing error correction encoding on (1) a first random sequence combined with a second random sequence, concatenated with (2) second metadata to obtain first encoded data;
performing error correction encoding on a sequence of zeros concatenated with the first error-corrected metadata in order to obtain second encoded data;
summing (1) the error-corrected data, (2) the first encoded data, and (3) the second encoded data in order to obtain migrated data; and
storing the migrated data at a second physical location in the storage.
12. The computer program product of claim 11 , wherein error correction encoding is performed on (1) the first random sequence combined with the second random sequence, concatenated with (2) the second metadata while error correction decoding is performed on the read data.
13. The computer program product of claim 11 , wherein the storage includes solid state storage.
14. The computer program product of claim 11 , wherein the computer instructions for performing error correction encoding and performing error correction decoding include computer instructions for using one or more of the following codes: a BCH code or a low-density parity-check (LDPC) code.