Granted Patent B2

US 10,120,753 · App. 14/721,913 · Granted Nov 6, 2018

Abstract

Claims (52)

1. An apparatus comprising:

a memory device having a plurality of multi-level cells;

an encoder circuit coupled to the memory device and configured to store a first plurality of data bits in first multi-level cells of the plurality of multi-level cells and to store a second plurality of data bits in second multi-level cells of the plurality of multi-level cells, and further configured to store parity check bits in the second multi-level cells with the second plurality of data bits, wherein the parity check bits are based on first parity bits and the second plurality of data bits and the first parity bits are based on second parity bits for the first plurality of data bits, and wherein the first and second plurality of data bits, and the parity check bits are stored in the plurality of multi-level cells in a tensor product code configuration; and

a decoder circuit coupled to the memory device and configured to identify one or more erroneous cells in the plurality of multi-level cells, erase data bits stored in the one or more erroneous cells, convert a flash channel associated with the plurality of multi-level cells from an errors channel to an erasures channel, and perform low density parity check decoding.

2. The apparatus of claim 1 , wherein the encoder circuit comprises:

a single parity check encoder circuit configured to calculate parity bits for a plurality of bits; and

a Bose-Chaudhuri-Hocquenghem (BCH) encoder configured to calculate a plurality of BCH parity bits.

3. The apparatus of claim 2 , wherein the encoder circuit comprises:

a storage device for storing at least some of the parity bits and the BCH parity bits.

4. The apparatus of claim 1 , wherein the decoder circuit comprises:

a single parity check decoder circuit configured to calculate parity bits for a plurality of bits; and

a BCH decoder circuit configured to identify erroneous cells in the memory device.

5. The apparatus of claim 1 , wherein the decoder circuit comprises a low density parity check decoder circuit configured to correct the one or more erroneous cells.

6. An apparatus comprising:

a memory device having a first plurality of data bits stored in first plurality of multi-level memory cells, a second plurality of data bits stored in a second plurality of multi-level memory cells, and further having parity check bits stored with the second plurality of data bits in the second plurality of multi-level memory cells, wherein the first and second plurality of data bits and the parity check bits are stored in the first and second plurality of multi-level cells in a tensor product code configuration; and

a controller coupled to the memory device and configured to identify one or more erroneous multi-level memory cells, erase data bits stored in the one or more erroneous multi-level memory cells, convert a flash channel associated with the plurality of multi-level memory cells from an errors channel to an erasures channel, and perform low density parity check decoding.

7. The apparatus of claim 6 , wherein the tensor product code configuration comprises the plurality of user bits and a plurality of tensor product code parity bits.

8. The apparatus of claim 7 , wherein the controller comprises:

an encoder circuit configured to generate a first BCH code word and the plurality of tensor product code parity bits for the plurality of multi-level memory cells; and

a decoder circuit configured to generate a second BCH code word based on the plurality of tensor product code parity bits.

9. A method comprising:

identifying one or more errors in a plurality of memory cells having a plurality of data bits encoded thereon in a tensor product code, wherein the tensor product code includes a first plurality of data bits stored in first memory cells of the plurality of memory cells, a second plurality of data bits stored in second memory cells of the plurality of memory cells, and parity check bits stored in the second memory cells of the plurality of memory cells with the second plurality of data bits, and wherein fewer data bits are stored in the second memory cells of the plurality of memory cells than the data bits stored in the first memory cells of the plurality of memory cells; and

erasing data bits stored in one or more erroneous cells of the plurality of memory cells, converting a flash channel associated with the plurality of memory cells from an errors channel to an erasures channel, and performing low density parity check decoding.

10. The method of claim 9 , wherein each of the plurality of memory cells is a multi-level cell.

11. The method of claim 9 , wherein the tensor product code comprises a single parity check code and a Bose-Chaudhuri-Hocquenghem code.

12. A method comprising:

storing a first set of data bits in a first plurality of memory cells; determining a first set of parity bits for the first plurality of memory cells; determining a Bose-Chaudhuri-Hocquenghem (BCH) parity bit for each of the parity bits in the first set of parity bits;

storing a second set of data bits in a second plurality of memory cells;

determining a second set of single parity check (SPC) parity-bits for the second set of data bits and the BCH parity bits;

storing the second set of single parity check (SPC) bits in the second plurality of memory cells;

decoding the second set of parity bits to generate a BCH code word; identifying one or more erroneous cells in the first and second plurality of memory cells based on the BCH code word;

erasing data bits stored in the one or more erroneous cells;

converting a flash channel associated with the first and second plurality of memory cells from an errors channel to an erasures channel; and

performing low density parity check decoding.

13. The method of claim 12 , wherein identifying the one or more one or more erroneous cells comprises:

comparing the BCH code word to the first set of parity bits and the BCH parity bits.

14. The method of claim 12 , wherein the first and second plurality of memory cells are multi-level cells.

15. A method comprising:

storing a first plurality of data bits in a first plurality of multi-level memory cells;

encoding the first plurality of bits according to a tensor product code to generate a first plurality of parity bits;

encoding a second plurality of data bits and the first plurality of parity bits according to the tensor product code to generate a second plurality of parity bits;

storing the second plurality of data bits and the second plurality of parity bits in a second plurality of multi-level memory cells;

identifying one or more erroneous cells in at least one of the first and second plurality of multi-level memory cells;

erasing data bits stored in the one or more erroneous cells;

converting a flash channel associated with the first and second plurality of multi-level memory cells from an errors channel to an erasures channel; and

performing low density parity check decoding.

16. The method of claim 15 , wherein the tensor product code comprises a single parity check code and a Bose-Chaudhuri-Hocquenghem code.

17. The method of claim 15 , wherein identifying the one or more erroneous cells comprises:

decoding the second plurality of data bits according to the tensor product code to generate a code word.

18. The method of claim 17 , wherein identifying the one or more erroneous cells further comprises:

comparing one or more bits in the code word to a corresponding bit in the first plurality of parity bits; and

identifying one or more differences between the one or more bits in the code word and the corresponding bits in the first plurality of parity bits.

Assignments (8)