Methods and structure for carrier-less thin wafer handling

1. A method of forming a microelectronic assembly, comprising: removing material exposed at portions of a surface of a substrate to form a processed substrate having a plurality of thinned portions separated by integral supporting portions of the processed substrate, the supporting portions having a thickness greater than a thickness of the thinned portions, the thinned portions including electrically conductive interconnects extending in a direction of the thickness of the thinned portions and exposed at the surface; forming a dielectric layer on the thinned portions; forming openings extending through the dielectric layer, the interconnects being exposed within the openings; depositing an electrically conductive material within the openings; and removing material of the processed substrate thereby planarizing a surface of the dielectric layer relative to at least one of the supporting portions or material of the processed substrate overlying the supporting portions.

2. The method of claim 1 , wherein prior to the step of depositing the electrically conductive material, further comprising:

depositing a metal layer overlying the dielectric layer and in conductive communication with the interconnects, wherein the metal layer comprises at least one of an adhesion layer or a barrier layer or a seed layer.

3. The method of claim 2 , wherein depositing the electrically conductive material further comprises:

depositing the electrically conductive material on the surfaces of the metal layer and within the openings.

4. The method of claim 3 , further comprising:

removing at least portions of the supporting portions of the substrate to sever the substrate into a plurality of individual thinned portions, the individual thinned portions including the interconnects.

5. The method of claim 4 , prior to removing the at least portions of the supporting portions, further comprising:

juxtaposing contacts at a surface of a microelectronic element with substrate contacts of the processed substrate and joining the contacts with the juxtaposed substrate contacts, wherein the substrate contacts are disposed above the surfaces of the electrically conductive material and in conductive communication with the electrically conductive material.

6. The method of claim 1 , wherein forming the dielectric layer further comprises:

forming a dielectric passivation layer overlying the surface of the thinned portions; and

forming a second dielectric layer overlying the surfaces of the dielectric passivation layer.

7. A method of forming a microelectronic assembly, comprising: removing material exposed at portions of a surface of a substrate to form a processed substrate having a plurality of thinned portions separated by integral supporting portions of the processed substrate, the supporting portions having a thickness greater than a thickness of the thinned portions, the thinned portions including electrically conductive interconnects extending in a direction of the thickness of the thinned portions and exposed at the surface; forming a dielectric layer on the thinned portions; forming openings extending through the dielectric layer, the interconnects being exposed within the openings; depositing an electrically conductive material within the openings; and removing material of the processed substrate thereby planarizing a surface of the dielectric layer relative to at least one of the supporting portions or material of the processed substrate overlying the supporting portions; forming a dielectric passivation layer overlying the surface of the thinned portions; forming a second dielectric layer overlying the surfaces of the dielectric passivation layer; and removing the second dielectric layer after the openings are formed and prior to depositing the electrically conductive material.

8. The method of claim 7 , wherein depositing the electrically conductive material further comprises:

depositing the electrically conductive material above the dielectric passivation layer and within the openings.

9. The method of claim 8 , prior to depositing the electrically conductive material, further comprising:

depositing a metal layer overlying the dielectric passivation layer and in conductive communication with the interconnects, wherein the metal layer comprises at least one of an adhesion layer or a barrier layer or a seed layer.

10. The method of claim 8 , further comprising:

forming a third dielectric layer overlying the electrically conductive material;

forming second openings extending through the third dielectric layer, the second openings overlying a portion of the electrically conductive material between the interconnects; and

removing the portion of the electrically conductive material exposed within the second openings to electrically isolate the interconnects from one another.

11. The method of claim 10 , further comprising:

removing the third dielectric layer after removing the portion of the electrically conductive material.

12. The method of claim 11 , further comprising:

removing the supporting portions of the substrate to sever the substrate into a plurality of individual thinned portions including the interconnects.

13. The method of claim 1 , wherein during the step of removing material at the surface of the substrate, at least some of the thinned regions are formed so as to leave supporting portions surrounding the at least some thinned regions.

14. The method of claim 1 , wherein removing the supporting portions further comprises:

sawing at least one first supporting portion of the substrate in a first direction and sawing at least one second supporting portion of the substrate in a second direction transverse to the first direction.