IP Library Granted Patent US 9,608,000
Granted Patent B2
US 9,608,000 · App. 14/722,824 · Granted Mar 28, 2017

Devices and methods including an etch stop protection material

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,608,000
App. No.
14/722,824
Granted
Mar 28, 2017
Kind
B2
Abstract

Protective dielectrics are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory may include a protective dielectric material. A device may include an etch stop material, a first control gate (CG) over the etch stop material, a first CG recess adjacent the first CG, a trench adjacent the first CG recess, and an at least partially oxidized polysilicon on at least a portion of the etch stop material. The at least partially oxidized polysilicon may line a sidewall of the trench and may line the first CG recess.

Claims (26)

1. A device comprising:

a first polysilicon material;

an etch stop material on the first polysilicon material;

a second polysilicon material on the etch stop material;

a first tier dielectric material on the second polysilicon material;

a first control gate over the etch stop material and on the first tier dielectric material;

a first control gate recess adjacent the first control gate;

a trench adjacent the first control gate recess;

an at least partially oxidized polysilicon on at least a portion of the etch stop material,

wherein the at least partially oxidized polysilicon lines a sidewall of the trench and lines the first control gate recess, the at least partially oxidized polysilicon in contact with the control gate;

a nitride in contact with the at least partially oxidized polysilicon and in the first control gate recess, the at least partially oxidized polysilicon between the nitride and the first control gate;

a dielectric in contact with the at least partially oxidized polysilicon and in the first control gate recess, the nitride between the dielectric and the at least partially oxidized polysilicon;

a floating gate in contact with the at least partially oxidized polysilicon and in the first control gate recess, the dielectric between the floating gate and the nitride; and

a tunnel oxide adjacent the floating gate.

2. The device of claim 1 , wherein the at least partially oxidized polysilicon includes a polysilicon at least partially oxidized using an in situ steam generation (ISSG) process.

3. The device of claim 1 , wherein the trench includes substantially vertical sidewalls.

4. The device of claim 1 , wherein the etch stop material includes aluminum oxide.

5. The device of claim 1 , further comprising:

a second tier dielectric on the first CG;

a second CG on the second tier dielectric;

a second CG recess adjacent the second CG; and

a third tier dielectric on the second CG;

wherein the trench is further adjacent to the third tier dielectric, second tier dielectric, second CG recess, and first tier dielectric; and

wherein the at least partially oxidized polysilicon further lines the second CG recess.

6. The device of claim 5 , wherein the device further comprises:

a second nitride material adjacent the oxidized polysilicon in the second CG recess, wherein the first and second nitride materials are electrically isolated from each other.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 5, 2016
From: HOPKINS, JOHN; FAN, DARWIN FRANSEDA
To: MICRON TECHNOLOGY, INC.
Reel/Frame 037675/0428 →