Power semiconductor package with a common conductive clip
According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to a common conductive clip, and a control gate for being driven by a driver IC. The stacked half-bridge package also includes a sync transistor having a sync drain for connection to the common conductive clip, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. The control and sync transistors are stacked on opposite sides of the common conductive clip with the common conductive clip electrically and mechanically coupling the control source with the sync drain, where the common conductive clip has a conductive leg for providing electrical and mechanical connection to an output terminal leadframe.
1. A power semiconductor package comprising:
a control transistor having a control drain for connection to a high voltage input, a control source coupled to a common conductive clip, and a control gate;
a sync transistor having a sync drain for connection to said common conductive clip, a sync source coupled to a low voltage input, and a sync gate;
said control and sync transistors being situated on opposite sides of said common conductive clip, said common conductive clip coupling said control source with said sync drain.
2. The power semiconductor package of claim 1 , wherein a conductive web of said common conductive clip provides said coupling of said control source with said sync drain.
3. The power semiconductor package of claim 1 , wherein a conductive leg of said common conductive clip is of a thickness greater than that of said control transistor.
4. The power semiconductor package of claim 1 , wherein a control drain leadframe provides connection for said control drain.
5. The power semiconductor package of claim 1 , wherein a conductive source clip provides connection between said sync source and a sync source leadframe.
6. The power semiconductor package of claim 5 , wherein said conductive source clip comprises a source clip leg that is of a thickness greater than that of said sync transistor.
7. The power semiconductor package of claim 1 , wherein a conductive source clip comprises a source clip web that is connected to said sync source and including a source clip leg that is connected to a sync source leadframe.
8. The power semiconductor package of claim 1 , wherein a conductive source clip is connected to said sync source at a topside of said stacked half-bridge package.
9. The power semiconductor package of claim 1 , wherein bottom surfaces of a sync source leadframe and a control drain leadframe are substantially flush with one another.
10. The power semiconductor package of claim 1 , wherein top surfaces of a sync source leadframe and a control drain leadframe are substantially flush with one another.
11. The power semiconductor package of claim 1 , wherein at least one control gate bondwire provides connection for said control gate.
12. The power semiconductor package of claim 11 , wherein said at least one control gate bondwire provides connection between said control gate and a control gate leadframe.
13. The power semiconductor package of claim 1 , wherein at least one sync gate bondwire provides connection for said sync gate.
14. The power semiconductor package of claim 13 , wherein said at least one sync gate bondwire provides connection between said sync gate and a sync gate leadframe.
15. The power semiconductor package of claim 1 , wherein said sync source comprises a plurality of sync source pads.
16. The power semiconductor package of claim 1 , wherein said control transistor has top and bottom surfaces, said control drain being on said bottom surface and said control source and said control gate being on said top surface.
17. The power semiconductor package of claim 1 , wherein said sync transistor has top and bottom surfaces, said sync drain being on said bottom surface and said sync source and said sync gate being on said top surface.
18. The power semiconductor package of claim 1 , wherein respective bottom surfaces of a sync source leadframe, a control drain leadframe, a sync gate leadframe, and a control gate leadframe are substantially flush with one another.
19. The power semiconductor package of claim 1 , wherein a sync source leadframe and a control drain leadframe are of substantially a same thickness.
20. The power semiconductor package of claim 1 , wherein a sync source leadframe, a control drain leadframe, a sync gate leadframe, and a control gate leadframe are of substantially a same thickness.