IP Library › Granted Patent US 10,152,310
Granted Patent B2
US 10,152,310 · App. 14/723,141 · Granted Dec 11, 2018

Fusing a sequence of operations through subdividing

Inventors: Mahesh Ravishankar (Redmond, WA); Paulius Micikevicius (Santa Clara, CA); Vinod Grover (Redmond, WA)
Assignee: Nvidia Corporation
G06F8/4434G06F8/45G06F8/41
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Quick Facts
Patent No.
US 10,152,310
App. No.
14/723,141
Granted
Dec 11, 2018
Kind
B2
Abstract

A compiler and a method of compiling code that reduces memory bandwidth when processing code on a computer are provided herein. In one embodiment, the method includes: (1) automatically identifying a sequence of operations for fusing, wherein the sequence of operations correspond to instructions from a source code, (2) determining subdivisions of a final output of the sequence of operations, (3) determining input data and intermediate operations needed to obtain a final subdivision output for each of the subdivisions and (4) automatically generating code to fuse the sequence of operations employing the subdivisions, wherein the automatically identifying and the automatically generating are performed by a processor.

Claims (34)

1. A method for compiling code to reduce memory bandwidth when processing code on a computer, comprising:

automatically identifying a sequence of operations for fusing, wherein said sequence of operations correspond to instructions from a source code;

determining subdivisions of a final output of said sequence of operations;

analyzing at least one of said subdivisions final output;

determining input data and intermediate operations, using said analyzing of said at least one of said subdivisions final output, needed to obtain a final subdivision output for each of said subdivisions;

automatically generating code to fuse said sequence of operations employing said subdivisions, wherein:

said automatically identifying and said automatically generating are performed by a processor; and

said automatically generating includes generating code to:

save said input data in a local memory;

perform said intermediate operations; and

save temporary results of said intermediate operations in said local memory; and

generating code to save said final subdivision output for each of said subdivisions in an external memory, wherein said saving said input data in said local memory, said saving said temporary results of said intermediate operations in said local memory, and saving said final subdivision output for each of said subdivisions in said external memory reduces said memory bandwidth independent of a skill of a programmer.

2. The method as recited in claim 1 wherein said sequence of operations is functions or computations to perform said instructions from said source code.

3. The method as recited in claim 1 wherein said automatically generating code is for a targeted computer architecture.

4. The method as recited in claim 1 wherein said sequence of operations is for a domain specific language.

5. The method as recited in claim 1 wherein said sequence of operations includes computations or functions for image processing.

6. The method as recited in claim 1 wherein said automatically identifying said sequence of operations for fusing is based on a producer-consumer relationship of said operations.

7. The method as recited in claim 1 wherein said automatically identifying said sequence of operations for fusing is based on a directed acyclic graph of said sequence of operations.

8. The method as recited in claim 1 wherein said sequence of operations is a sequence of convolution kernels for a graphics processing pipeline.

9. A computer program product including a series of operating instructions stored on a non-transitory computer readable medium that directs a processor to perform a method to generate executable code for operation on a computer system, wherein the method comprises:

automatically identifying a sequence of operations for fusing, wherein said sequence of operations correspond to instructions from a source code;

determining subdivisions of a final output of said sequence of operations;

analyzing a final subdivision output of each of said subdivisions;

determining, using said analyzing, input data and intermediate operations needed to obtain said final subdivision output for each of said subdivisions;

automatically generating executable code for operation on a particular computer architecture, wherein said executable code fuses said sequence of operations employing said subdivisions, wherein said automatically generating includes generating code to:

save said input data in a local memory;

perform said intermediate operations; and

save temporary results of said intermediate operations in said local memory; and

generating code to save said final subdivision output for each of said subdivisions in an external memory, wherein said saving said input data in said local memory, saving said temporary results of said intermediate operations in said local memory, and saving said final subdivision output for each of said subdivisions in said external memory reduces memory bandwidth independent of a skill of a programmer.

10. The computer program product as recited in claim 9 wherein said sequence of operations is functions or computations of a domain specific language that direct a processor of said computer architecture to implement said instructions from said source code.

11. The computer program product as recited in claim 9 wherein said automatically identifying said sequence of operations for fusing is based on a producer-consumer relationship of said operations.

12. The computer program product as recited in claim 9 wherein said automatically identifying said sequence of operations for fusing is based on a directed acyclic graph of said sequence of operations.

13. The computer program product as recited in claim 9 wherein said sequence of operations is a sequence of convolution kernels for a graphics processing pipeline.

14. The computer program product as recited in claim 9 wherein said sequence of operations includes computations or functions for image processing.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 25, 2015
From: RAVISHANKAR, MAHESH; MICIKEVICIUS, PAULIUS; GROVER, VINOD
To: NVIDIA CORPORATION
Reel/Frame 035904/0909 →
Continuity (1)
Related Publication 20160350088A1 · Dec 1, 2016