Vector processor configured to operate on variable length vectors using one or more complex arithmetic instructions

1. A processor, comprising:

a vector register file comprising vector registers to hold complex elements, wherein each one of the complex elements is a data item comprising a real part and an imaginary part, and each one of the real part and the imaginary part is represented by one or more bits;

a length register file comprising a length register to store an integer value L representing a number of operations; and

a processing logic to implement a variable length vector instruction comprising one or more complex arithmetic instructions, the variable length vector instruction comprising:

a first field comprising identifiers of one or more vector registers in the vector register file holding a varying number of complex elements; and

a second field comprising an identifier of the length register to store the integer value L representing the number of operations applied to the varying number of complex elements held in the one or more vector registers, wherein the number of operations is independent from a number of complex elements packed in the one or more vector registers, and wherein the number of operations stored in the length register is larger than a number of complex elements that each of the one or more vector registers is able to hold in a hardware implementation.

2. The processor of claim 1 , wherein the number of operations is one of different than or same as the number of complex elements held in the one or more vector register, and wherein the processor is implemented as a monolithic integrated circuit.

3. The processor of claim 1 , wherein the length register file comprises a second length register to specify a number of complex elements packed in the one or more vector registers.

4. The processor of claim 1 , wherein the varying number of complex elements are stored in the one or more vector registers as a sequence of alternating real parts and imaginary parts, wherein a pair of a real part and an imaginary part constitute a complex element.

5. The processor of claim 1 , wherein the processing logic is further to read a first vector and a second vector from the one or more vector registers, treat contents of the first vector and the second vector as vectors of complex elements, element-wise multiply the complex elements from the first vector register with the second vector register to produce a resulting vector of complex elements, and store the resulting vector of complex elements to the vector register file.

6. The processor of claim 1 , wherein the processing logic is further to read three vectors from the one or more vector registers, treat contents of the three vectors as vectors of complex elements, element-wise multiply the complex elements from a first vector register with a second vector register to produce a product, add the product to a third vector to produce a third vector of complex vectors, and store the third vector to the vector register file.

7. The processor of claim 1 , wherein the processing logic is further to read a first vector and a second vector from the one or more vector registers, treat contents of the first vector and the second vector as vectors of complex elements, element-wise multiply the complex elements from the first vector register with the second vector register, and sum together the resulting products to produce a single complex number.

8. The processor of claim 7 , further comprising an accumulator register file comprising one or more accumulator registers to store the single complex number.

9. The processor of claim 7 , further comprising a floating point register file comprising two or more floating point registers, wherein the single complex number is stored to two floating point registers of the two or more floating point registers.

10. The processor of claim 7 , further comprising a general purpose register file comprising two or more general purpose registers to store the single complex number.

11. The processor of claim 1 , wherein the processing logic is further to read two vectors from the one or more vector registers, treat contents of the two vector registers as vectors of complex elements, element-wise multiply the complex elements from a first vector register with a second vector register to produce resulting products, and sum the resulting products with an input single complex number to produce a single complex number.

12. The processor of claim 11 , further comprising an accumulator register file comprising one or more accumulator registers, wherein the input single complex number is read from an accumulator register of the one or more accumulator registers, and wherein the single complex number is stored to the accumulator register file.

13. The processor of claim 11 , further comprising a floating point register file comprising two or more floating point registers, wherein the input complex number is read from two floating registers of the two or more floating point registers, and wherein the single complex number is stored to the two floating point registers of the two or more floating point registers.

14. The processor of claim 11 , further comprising a general purpose register file comprising two or more general purpose registers, wherein the single complex number is read from the two general purpose registers of the two or more general purpose registers, and wherein the single complex number is stored to the two general purpose registers of the two or more general purpose registers.

15. The processor of claim 1 , wherein the processing logic is further to read two vectors from the one or more vector registers, treat contents of the two vectors as vectors of complex elements, element-wise multiply the complex numbers from a first vector register with a second vector register, split the resulting products into groups, sum the complex elements of products of each group to produce a vector of complex elements, and store the vector of complex elements to the vector register file.

16. The processor of claim 1 , wherein the processing logic is further to read a vector from the one or more vector registers, treat contents of the one or more vector as the complex elements, and sum the complex elements to produce a single complex number.

17. The processor of claim 1 , wherein the processing logic is further to read a vector from the one or more vector registers, treat contents of the vector as the complex elements, and sum together the complex elements with a single input complex number to produce a single complex number.

18. The processor of claim 17 , further comprising an accumulator register file comprising one or more accumulator registers, wherein the single complex number is read from an accumulator register of the one or more accumulator registers, and wherein the single complex number is stored to the accumulator register file.

19. The processor of claim 17 , further comprising a floating point register file comprising two or more floating point registers, wherein the single complex number is read from two floating registers of the two or more floating point registers, and wherein the single complex number is stored to the two floating point registers of the two or more floating point registers.

20. The processor of claim 17 , further comprising a general purpose register file comprising two or more general purpose registers, wherein the single complex number is read from two general purpose registers of the two or more general purpose registers, and wherein the single complex number is stored to the two general purpose registers of the two or more general purpose registers.

21. The processor of claim 1 , wherein the processing logic is further to read a vector from the one or more vector registers, treat contents of the vector as the complex elements, divide the vector elements into groups, and sum together the complex elements in each group to produce a corresponding vector of complex number, and store the vector of complex elements to the vector register file.

22. A method comprising:

storing, by a processing logic of a processor, in vector registers in a vector register file, complex elements, wherein each one of the complex elements is a data item comprising a real part and an imaginary part, and wherein each one of the real part and the imaginary part is represented by one or more bits;

storing, by the processing logic, an integer value L representing a number of operations in a length register of a length register file; and

executing, by the processing logic, a variable length vector instruction comprising one or more complex arithmetic instructions, the variable length vector instruction comprising:

a first field comprising identifiers of one or more vector registers in the vector register file holding a varying number of complex elements; and

a second field comprising an identifier of the length register store the integer value L representing the number of operations applied to the varying number of complex elements held in the one or more vector registers, wherein the number of operations is independent from a number of complex elements packed in the one or more vector registers, and wherein the number of operations stored in the length register is larger than a number of complex elements that each of the one or more vector registers is able to hold in a hardware implementation.

23. The method of claim 22 , wherein the number of operations is one of different than or same as the number of complex elements held in the one or more vector register, and wherein the processor is implemented as a monolithic integrated circuit.

24. The method of claim 22 , wherein the length register file comprises a second length register to specify a number of complex elements packed in the one or more vector registers.

25. The method of claim 24 , wherein the varying number of complex elements are stored in the one or more vector registers as a sequence of alternating real parts and imaginary parts, wherein a pair of a real part and an imaginary part constitute a complex element.

26. The method of claim 22 , further comprising reading, by the processing logic, a first vector and a second vector from the one or more vector registers, treating contents of the first vector and the second vector as vectors of complex elements, element-wise multiplying the complex elements from the first vector register with the second vector register to produce a resulting vector of complex elements, and storing the resulting vector of complex elements to the vector register file.

27. The method of claim 22 , further comprising reading, by the processing logic, three vectors from the one or more vector registers, treating contents of the three vector registers as vectors of complex elements, element-wise multiplying the complex elements from a first vector register with a second vector register to produce a product, adding the product to the third vector to produce a third vector of complex vectors, and storing the third vector to the vector register file.

28. The method of claim 22 , further comprising reading, by the processing logic, a first vector and a second vector from the one more vector registers, treating contents of the first vector and the second vector as vectors of complex elements, element-wise multiplying the complex elements from the first vector register with the second vector register, and summing together the resulting products to produce a single complex number.

29. The method of claim 28 , wherein the processor further comprises an accumulator register file comprising one or more accumulator registers, and further comprising storing the single complex number to the accumulator register file.

30. The method of claim 28 , wherein the processor further comprises a floating point register file comprising two or more floating point registers, and further comprising storing the single complex number to the two floating point registers of the two or more floating point registers.

31. The method of claim 28 , wherein the processor further comprises a general purpose register file comprising two or more general purpose registers, and further comprising storing the single complex number to the two general purpose registers of the two or more general purpose registers.

32. The method of claim 22 , further comprising reading, by the processing logic, two vectors from the one or more vector registers, treating contents of the two vector registers as vectors of complex elements, element-wise multiplying the complex elements from a first vector register with a second vector register to produce resulting products, and summing the resulting products with an input single complex number to produce a single complex number.

33. The method of claim 32 , further comprising an accumulator register file comprising one or more accumulator registers, and further comprising reading the input single complex number from an accumulator register of the one or more accumulator registers, and storing the single complex number to the accumulator register file.

34. The method of claim 32 , wherein the floating point register file comprises two or more floating point registers, and further comprising reading the input complex number from two floating registers of the two or more floating point registers, and storing the single complex number to the two floating point registers of the two or more floating point registers.

35. The method of claim 32 , wherein the processor further comprises a general purpose register file comprising two or more general purpose registers, and further comprising reading the single complex number from two general purpose registers of the two or more general purpose registers, and storing the single complex number to the two general purpose registers of the two or more general purpose registers.

36. The method of claim 22 , further comprising reading, by the processing logic, two vectors from the one or more vector registers, treating contents of the two vectors as vectors of complex elements, element-wise multiplying the complex numbers from a first vector register with a second vector register, splitting the resulting products into groups, summing the complex elements of products of each group to produce a vector of complex elements numbers, and storing the vector of complex elements to the vector register file.

37. The method of claim 22 , further comprising reading, by the processing logic, a vector from the one or more vector registers, treating the contents of the vector as the complex elements, and summing the complex elements to produce a single complex number.

38. The method of claim 22 , further comprising reading, by the processing logic, a vector from the one or more vector registers, treating contents of the vector as the complex elements, and summing the complex elements with a single input complex number to produce a single complex number.

39. The method of claim 38 , wherein the processor further comprises an accumulator register file comprising one or more accumulator registers, and further comprising reading the single complex number from an accumulator register of the one or more accumulator registers, and storing the single complex number to the accumulator register file.

40. The method of claim 38 , wherein the floating point register file comprises two or more floating point registers, and further comprising reading the single complex number from two floating registers of the two or more floating point registers, and storing the single complex number to the two floating point registers of the two or more floating point registers.

41. The method of claim 38 , wherein the processor comprises a general purpose register file comprising two or more general purpose registers, and further comprising reading the single complex number from two general purpose registers of the two or more general purpose registers, and storing the single complex number to the two general purpose registers of the two or more general purpose registers.

42. The method of claim 22 , further comprising reading, by the processing logic, a vector from the one or more vector registers, treating contents of the vector as the complex elements, dividing the vector numbers into groups, summing the complex numbers in each group to produce a corresponding vector of complex number, and storing the vector of complex numbers to the vector register file.