Systems and methods for throttling packet transmission in a scalable memory system protocol
A method may include transmitting, via a processor, a plurality of packets to a receiving component, such that the plurality of packets corresponds to a plurality of data operations configured to access a memory component. The plurality of packets is stored in a buffer of the receiving component upon receipt. The method may also include determining, via the processor, whether an available capacity of the buffer is less than a threshold, decreasing a transmission rate of the plurality of packets when the available capacity is less than the threshold.
1. A memory device comprising:
a memory component configured to store data;
a buffer;
a processor configured to execute one or more computer-executable instructions that cause the processor to:
receive a plurality of packets from a requesting component, wherein the plurality of packets corresponds to a plurality of data operations configured to access the memory component, and wherein the plurality of packets is stored in the buffer;
monitor an available capacity of the buffer;
determine whether the available capacity of the buffer is less than a threshold; and
send a message to the requesting component when the available capacity is less than the threshold, wherein the message comprises instructions for the requesting component to decrease a transmission rate of the plurality of packets based on a transaction window of each of the plurality of packets, wherein the transaction window comprises information indicating a type of memory component associated with a data operation of a respective packet of the plurality of packets.
2. The memory device of claim 1 , wherein the threshold corresponds to 90% of a total capacity of the buffer.
3. The memory device of claim 1 , wherein the instructions cause the requesting component to decrease the transmission rate according to a linear function.
4. The memory device of claim 3 , wherein the transmission rate is directly related to the available capacity.
5. The memory device of claim 1 , wherein the instructions cause the requesting component to decrease the transmission rate according to a non-linear function.
6. The memory device of claim 1 , wherein the instructions cause the requesting component to decrease the transmission rate according to a step down function.
7. A system, comprising:
a requesting component;
a memory device comprising:
a buffer;
a processor configured to execute one or more computer-executable instructions that cause the processor to:
receive a plurality of packets from the requesting component, wherein the plurality of packets corresponds to a plurality of data operations configured to access the memory device, and wherein the plurality of packets is stored in the buffer;
monitor an available capacity of the buffer;
determine whether the available capacity of the buffer is less than a threshold; and
send a message to the requesting component when the available capacity is less than the threshold, wherein the message comprises instructions for the requesting component to decrease a transmission rate of the plurality of packets based on a transaction window of each of the plurality of packets, wherein the transaction window comprises information indicating a type of memory component associated with a data operation of a respective packet of the plurality of packets.
8. The system of claim 7 , wherein the buffer is a first-in-first-out buffer.
9. The system of claim 7 , wherein the processor is configured to send the message to the requesting component when the buffer is full.
10. The system of claim 7 , wherein the processor is configured to send the message when an outstanding transaction count associated with a number of a portion of the plurality of packets stored in the buffer exceeds a first value.
11. The system of claim 10 , wherein the processor is configured to receive the first value via input from a user of the system.
12. The system of claim 7 , wherein the processor is configured to send the message when the transmission rate exceeds a first value.
13. The system of claim 12 , wherein the processor is configured to receive the first value via input from a user of the system.
14. A method comprising:
transmitting, via a processor, a plurality of packets to a receiving component, wherein the plurality of packets corresponds to a plurality of data operations configured to access a memory component, and wherein the plurality of packets is stored in a buffer of the receiving component upon receipt; and
decreasing, via the processor, a transmission rate of the plurality of packets based upon receipt of a message from the receiving component, wherein the message comprises instructions to decrease a transmission rate of the plurality of packets based on a transaction window of each of the plurality of packets, wherein the transaction window comprises information indicating a type of memory component associated with a data operation of a respective packet of the plurality of packets, and wherein the receiving component is configured to generate the message when an available capacity of the buffer is less than a threshold.
15. The method of claim 14 , wherein determining whether the available capacity is less than the threshold comprises:
receiving, via the processor, information regarding an expected packet processing rate for the receiving component; and
determining whether the transmission rate exceeds the expected packet processing rate; and
decreasing, via the processor, the transmission rate when the transmission rate exceeds the expected packet processing rate.
16. The method of claim 14 , wherein the message requesting that the transmission rate of the plurality of packets be decreased is received when the transmission rate exceeds an expected packet processing rate by the receiving component.
17. The method of claim 14 , wherein the transmission rate is decreased according to a linear function.
18. The method of claim 14 , wherein the transmission rate is decreased according to a non-linear function.