IP Library › Granted Patent US 9,570,568
Granted Patent B2
US 9,570,568 · App. 14/724,538 · Granted Feb 14, 2017

Semiconductor component and method for fabricating the same

Inventors: Cheng-Chieh Lai (New Taipei, TW); Kuang-Hsin Chen (Taoyuan, TW); Shih-Kai Fan (Hsinchu, TW); Yung-Hsien Wu (Hsinchu, TW); Yu-Hsun Chen (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
H01L29/42364H01L21/28026H01L27/0886H01L29/41791H01L29/66795H01L29/785
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Quick Facts
Patent No.
US 9,570,568
App. No.
14/724,538
Granted
Feb 14, 2017
Kind
B2
Abstract

A semiconductor component, which includes a substrate, an interfacial layer disposed on the substrate, a first metal gate structure and a second metal gate structure disposed on the substrate. The first metal gate structure includes a first high-k dielectric layer disposed on the interfacial layer, and a first metal gate layer disposed on the first high-k dielectric layer. The second metal gate structure includes a second high-k dielectric layer disposed on the interfacial layer, a third high-k dielectric layer disposed on the second high-k dielectric layer, and a second metal gate layer disposed on the third high-k dielectric layer.

Claims (48)

1. A semiconductor component, comprising:

a substrate;

an interfacial layer disposed on the substrate;

a first metal gate structure disposed on the substrate, comprising:

a first high-k dielectric layer disposed on the interfacial layer;

a first barrier layer in contact with the first high-k dielectric layer; and

a first metal gate layer disposed on the first barrier layer; and

a second metal gate structure disposed on the substrate, comprising:

a second high-k dielectric layer disposed on the interfacial layer;

a third high-k dielectric layer disposed on the second high-k dielectric layer, wherein the second high-k dielectric layer is between the third high-k dielectric layer and the interfacial layer, and the first high-k dielectric layer and the third high-k dielectric layer are made of different materials; and

a second metal gate layer disposed on the third high-k dielectric layer.

2. The semiconductor component of claim 1 , wherein a dielectric constant of the second high-k dielectric layer is greater than a dielectric constant of the third high-k dielectric layer.

3. The semiconductor component of claim 1 , wherein the first high-k dielectric layer and the second high-k dielectric layer are made of the same material.

4. The semiconductor component of claim 1 , further comprising a first work function metal layer disposed on the first barrier layer.

5. The semiconductor component of claim 1 , further comprising a second work function metal layer disposed on the third high-k dielectric layer.

6. The semiconductor component of claim 5 , further comprising a second barrier layer disposed between the third high-k dielectric layer and the second work function metal layer.

7. The semiconductor component of claim 1 , wherein the second metal gate structure comprises a second barrier layer in contact with the third high-k dielectric layer.

8. The semiconductor component of claim 7 , wherein the first barrier layer and the second barrier layer are made of the same material.

9. A semiconductor component, comprising:

a plurality of first devices, each of the plurality of the first devices comprising:

a first source;

a first drain; and

a first metal gate structure disposed between the first source and the first drain, the first metal gate structure comprising:

a first high-k dielectric layer; and

a first metal gate layer disposed on the first high-k dielectric layer; and

a plurality of second devices, each of the plurality of the second devices comprising:

a second source;

a second drain; and

a second metal gate structure disposed between the second source and the second drain, the second metal gate structure comprising:

a second high-k dielectric layer;

a third high-k dielectric layer disposed on the second high-k dielectric layer; and

a second metal gate layer disposed on the third high-k dielectric layer, wherein a number of the plurality of the first devices is greater or less than a number of the plurality of the second devices.

10. The semiconductor component of claim 9 , wherein a threshold voltage of at least one of the plurality of the first devices is different from a threshold voltage of at least one of the plurality of the second devices.

11. The semiconductor component of claim 9 , wherein the plurality of the first devices and the plurality of the second devices are FinFET devices.

12. The semiconductor component of claim 9 , wherein each of the plurality of the first devices further comprises a first work function metal layer disposed between the first high-k dielectric layer and the first metal gate layer.

13. The semiconductor component of claim 9 , wherein each of the plurality of the second devices further comprises a second work function metal layer disposed between the third high-k dielectric layer and the second metal gate layer.

14. The semiconductor component of claim 9 , wherein a material of the first high-k dielectric layer is the same as a material of the second high-k dielectric layer.

15. The semiconductor component of claim 9 , wherein a material of the first high-k dielectric layer is the same as a material of the third high-k dielectric layer.

16. A method for fabricating a semiconductor component, comprising:

forming an interfacial layer on a substrate;

forming a first high-k dielectric layer on the interfacial layer;

forming a second high-k dielectric layer on a first part of the first high-k dielectric layer, wherein the first part of the first high-k dielectric layer is between the second high-k dielectric layer and the interfacial layer;

forming a barrier layer on the second high-k dielectric layer and directly on a second part of the first high-k dielectric layer; and

forming a metal gate layer on the barrier layer.

17. The method of claim 16 , wherein a dielectric constant of the first high-k dielectric layer is greater than a dielectric constant of the second high-k dielectric layer.

18. The method of claim 16 , wherein a dielectric constant of the first high-k dielectric layer is less than a dielectric constant of the second high-k dielectric layer.

19. The method of claim 16 , further comprising forming a work function metal layer between the barrier layer and the metal gate layer.

20. The method of claim 19 , wherein the barrier layer, the work function metal layer, and the metal gate layer form a metal gate structure of a FinFET device.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 30, 2015
From: LAI, CHENG-CHIEH; CHEN, KUANG-HSIN; FAN, SHIH-KAI; WU, YUNG-HSIEN; CHEN, YU-HSUN
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 035941/0099 →
Continuity (1)
Related Publication 20160351673A1 · Dec 1, 2016