IP Library Granted Patent US 9,514,813
Granted Patent B2
US 9,514,813 · App. 14/724,909 · Granted Dec 6, 2016

Resistive memory device, resistive memory system, and operating method thereof

Inventors: Yong-kyu Lee (Hwaseong-si, KR); Yeong-taek Lee (Seoul, KR); Dae-seok Byeon (Seongnam-si, KR); In-gyu Baek (Seoul, KR); Man Chang (Seoul, KR); Lijie Zhang (Suwon-si, KR)
Assignee: Samsung Electronics Co., Ltd.
G11C13/0069G11C7/04G11C11/1675G11C13/0097G11C2013/0073G11C2013/0088G11C2013/0092
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Quick Facts
Patent No.
US 9,514,813
App. No.
14/724,909
Granted
Dec 6, 2016
Kind
B2
Abstract

A method for operating a memory device includes sensing a temperature of the resistive memory device, setting a level of a set voltage or current for writing to a memory cell based on the temperature, setting a level of a reset voltage for reset writing to the memory cell based on the temperature, and performing a write operation on the memory cell based on the level of the set voltage or current and the level of the reset voltage. The memory device may be a resistive memory device.

Claims (55)

1. A method of operating a resistive memory device, the method comprising:

sensing a temperature of the resistive memory device;

setting a level of a set voltage or a set current for writing to a memory cell based on the temperature;

setting a level of a reset voltage for reset writing to the memory cell based on the temperature; and

performing a write operation on the memory cell based on the level of the set voltage or the set current and the level of the reset voltage.

2. The method as claimed in claim 1 , wherein:

in the set writing, a resistance value of the memory cell varies according to the level of the set current flowing in the memory cell, and

in the reset writing, the resistance value of the memory cell varies according to the level of the reset voltage applied to the memory cell.

3. The method as claimed in claim 1 , further comprising:

adjusting at least one of the level of the set voltage or the level of the reset voltage based on the temperature and a first control signal; and

adjusting the level of the set current based on the temperature and a second control signal.

4. The method as claimed in claim 1 , further comprising:

decreasing the level of the reset voltage when the temperature increases, and

increasing the level of the reset voltage when the temperature decreases.

5. The method as claimed in claim 1 , further comprising:

decreasing the level of the set current when the temperature increases, and

increasing the level of the set current when the temperature decreases.

6. The method as claimed in claim 5 , further comprising:

adjusting the level of the set voltage to maintain a substantially constant value when the temperature changes.

7. The method as claimed in claim 1 , further comprising:

adjusting the level of the set current to maintain a substantially constant value when the temperature changes.

8. The method as claimed in claim 1 , wherein performing the write operation on the memory cell includes:

performing a set write operation on a first tile of the resistive memory device based on a level-adjusted set voltage or set current; and

performing a reset write operation on a second tile of the resistive memory device based on a level-adjusted reset voltage.

9. The method as claimed in claim 8 , further comprising performing the set write operation and the reset write operation simultaneously.

10. The method as claimed in claim 1 , further comprising:

generating a first sensing signal indicating that the temperature is less than a normal state, or generating a second sensing signal indicating that the temperature is greater than the normal state, and

setting a write condition to a cold state or a write condition to a hot state based on the first sensing signal or the second sensing signal, respectively.

11. The method as claimed in claim 10 , wherein:

adjusting levels of the set voltage, the set current, and the reset voltage to perform the write operation at a first operating voltage when the write condition is set to the hot state, and

adjusting the levels of the set voltage, the set current, and the reset voltage to perform the write operation at a second operating voltage when the write condition is set to the cold state, the second operating voltage greater than the first operating voltage.

12. A resistive memory device, comprising:

a memory cell array including a plurality of memory cells;

a power generator to provide a set voltage and a reset voltage;

a current controller to adjust a level of a set current;

a temperature sensor to sense a temperature of the memory cell array; and

control logic to control a write operation for the memory cells based on the set current or voltage and the reset voltage, wherein the current controller is to adjust the level of the set current for set writing to the memory cells based on the temperature and wherein the control logic is to adjust a level of a reset voltage for reset writing to the memory cells based on the temperature.

13. The device as claimed in claim 12 , wherein the control logic is to generate a first control signal to control the power generator and a second control signal to control the current controller based on the temperature.

14. The device as claimed in claim 12 , wherein the current controller is to:

decrease the level of the set current when the temperature increases, and

increase the level of the set current when the temperature decreases.

15. The device as claimed in claim 12 , wherein the control logic is to:

decrease the level of the reset voltage when the temperature increases, and

increase the level of the reset voltage when the temperature decreases.

16. An apparatus, comprising:

an interface; and

control logic to receive signals from or output signals to the interface, wherein the control logic is to control a write operation for a memory cell based on a set current or a set voltage and a reset voltage, and wherein the control logic is to adjust a level of the set current or the set voltage for set writing to the memory cell and a level of a reset voltage for reset writing to the memory cell based on a temperature of a memory device including the memory cell.

17. The apparatus as claimed in claim 16 , wherein the control logic is to:

decrease the level of the set current when the temperature increases, and

increase the level of the set current when the temperature decreases.

18. The apparatus as claimed in claim 16 , wherein the control logic is to:

decrease the level of the reset voltage when the temperature increases, and

increase the level of the reset voltage when the temperature decreases.

19. The apparatus as claimed in claim 16 , wherein the control logic is to adjust the level of the set voltage to maintain a substantially constant value when the temperature changes.

20. The apparatus as claimed in claim 16 , wherein the control logic is to adjust the level of the set current to maintain a substantially constant value when the temperature changes.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2015
From: LEE, YONG-KYU; LEE, YEONG-TAEK; BYEON, DAE-SEOK; BAEK, IN-GYU; CHANG, MAN; ZHANG, LIJIE
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 035739/0932 →
Priority Claims (1)
KR 10-2014-0132496 · Oct 1, 2014 · national
Continuity (1)
Related Publication 20160099052A1 · Apr 7, 2016