Segmented DAC

1. A segmented digital to analog converter comprising first, second and third segments, wherein:

the first segment (DAC1) comprises a plurality of impedances ( 52 . 1 to 52 .S 1 ) arranged in series;

the second segment (DAC2) comprises a plurality of current sources ( 62 . 1 to 62 .S 3 ) or a current divider;

the third segment (DAC3) comprises a current divider ( 72 ); and

a controller ( 20 ) arranged to receive an input digital word and to provide first, second and third control words to the first, second and third segments, respectively, such that the first second and third segments cooperate to provide an analog representation of the input digital word.

2. A segmented digital to analog converter as claimed in claim 1 , in which the first segment comprises S1 substantially matched resistances ( 52 . 1 to 52 .S 1 ) arranged in series and S1+1 ( 54 . 0 to 54 .S 1 ) switches, each having first and second terminals, the S1 series connected resistances defining 1+S1 nodes ( 56 . 0 to 56 .S 1 ) labelled 0 to S1, and where the 0th node is connected to a first reference voltage, and each of the 0th to S1th nodes are in communication with the second terminals of a respective one of the switches.

3. A segmented digital to analog converter as claimed in claim 2 where S1 is equal to 2 M , where M is an integer.

4. A segmented digital to analog converter as claimed in claim 2 , in which the first terminals of the even numbered ones of the switches ( 54 . 0 , 54 . 2 , 54 . 4 , . . . ) are connected to a first shared switch node ( 110 ), and the first terminals of the even numbered ones of the switches ( 54 . 1 , 54 . 3 , 54 . 5 , . . . ) are connected to a second shared switch node ( 112 ).

5. A segmented digital to analog converter as claimed in claim 4 , in which:

the second segment comprises a current source array and a current steering circuit, the second segment having three outputs and being operable to control current flow at the first, second and third outputs thereof in response to a second segment control word;

the third segment is a current steering digital to analog converter having two outputs and comprising a current divider and a current steering circuit, and is operable to control a ratio of current flow at the first and second outputs in response to a third segment control word; and

the first output of the second segment is arranged to supply a current input of the third segment; a second output of the second segment is operably connected to one of the first and second shared nodes and the third output of the second segment is operably connected to the other one of the first and second shared nodes; and

the first output of the third segment is operably connected to one of the first and second shared nodes and the second output of the third segment is operably connected to the other one of the first and second shared nodes.

6. A segmented digital to analog converter as claimed in claim 1 , in which the second segment comprises at least one current source and a current control network such that current can be selectively sent to at least first and second segment output nodes.

7. A segmented digital to analog converter as claimed in claim 6 , in which the second segment comprises S3 current sources each with a respective current steering circuit to direct the current from each one of the current sources to the second segment output nodes.

8. A segmented digital to analog converter as claimed in claim 1 in which at least one of the second and third segments has a current input for receiving an input current and further comprises a current divider to divide the input current into portions and a current steering circuit operable to selectively send portions of the input current to at least first and second outputs in response to a control word.

9. A segmented digital to analog converter as claimed in claim 1 , in which the resistor string is the main sub-DAC which converts the most significant part of the input word.

10. A segmented digital to analog converter as claimed in claim 1 , in which the controller ( 20 ) is arranged to such that once the current steering circuit of the third segment (DAC3) is steering all of the current from a current source ( 62 ) to one output node ( 110 , 112 ), and as a response to the increase of the digital input by 1 code, the controller ( 20 ) disconnects that current source ( 62 ) which had been providing all of the current to the third segment from the third segment and connects the current source to the resistor string thereby changing the value of the intermediate word (dp) by one, and a subsequent current source is connected to the third segment, and the outputs of the third segment are diverted to a node of the first segment where the current now being divided by the third segment had previously been in current flow communication.

11. A segmented digital to analog converter as claimed in claim 10 , in which the controller ( 20 ) is arranged to such that once the value of the control word (dp) for the second segment (DAC2) is at a maximum or minimum value, the value of the control word dm is incremented or decremented as a response to the increase or decrease of the digital input by 1 code, respectively, and the lower or upper tap, respectively, of the resistor string in the first segment (DAC1) is opened and an adjacent (subsequent or preceding, respectively) tap is closed.

12. A segmented digital to analog converter as claimed in claim 10 in which a number of current sources J1 and J2 connected to the first and second shared nodes are given by J1=dp and J2=2 P −1−dp or vice versa.

13. A segmented digital to analog converter as claimed in claim 1 in which at least one of the second and third segments is associated with at least one cascode transistor.

14. A segmented digital to analog converter as claimed in claim 13 further comprising switches operable to supply a current to the at least one cascode transistor to maintain the at least one cascode transistor in proper operating conditions irrespective of the digital code being converted.

15. A segmented digital to analog converter as claimed in claim 14 in which “dummy currents” are created by current sources, and are operable to be supplied to the cascode that would otherwise be non-conducting when an associated segment is either at zero or at a full scale value.

16. A segmented digital to analog converter as claimed in claim 1 , in which bias voltages for biasing at least one of : a) current sources of the second segment; and b) the current divider of the third segment; are formed by passing a current through a reference resistor, where the reference resistor is formed of the same material as the resistors of the first segment.

17. A segmented digital to analog converter as claimed in claim 1 , in which the second segment is the main sub-DAC that converts the most significant part of the input word.

18. A segmented digital to analog converter as claimed in claim 17 , in which the second segment has a first output node operably connected to an output node of the digital to analog converter, and the series connected impedances of the first segment are operably connected between the output node of the digital to analog converter and a node at a reference voltage; and a second output of the second segment is arranged to provide current to the third segment.

19. A segmented digital to analog converter as claimed in claim 18 , in which the third segment has a first output operatively connected to the output node of the digital to analog converter; and a second output arranged to supply current to a selected tap of a plurality of taps in the series connected impedances of the first segment.

20. A segmented digital to analog converter as claimed in claim 18 , in which the second and third segments each have a third output coupled to the reference voltage of the first segment.

21. A segmented digital to analog converter as claimed in claim 17 further comprising switches operable to supply a current to the at least one cascode transistor to maintain the at least one cascode transistor in proper operating conditions irrespective of the digital code being converted.

22. A segmented digital to analog converter as claimed in claim 1 comprising at least one further segment.

23. A segmented digital to analog converter as claimed in claim 1 , on which the digital to analog converter is monotonic in use.

24. A segmented digital to analog converter as claimed in claim 1 , further comprising an output buffer or an output amplifier.