IP Library Granted Patent US 9,502,101
Granted Patent B2
US 9,502,101 · App. 14/725,749 · Granted Nov 22, 2016

Two-part programming methods

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Quick Facts
Patent No.
US 9,502,101
App. No.
14/725,749
Granted
Nov 22, 2016
Kind
B2
Abstract

A first memory cell is programmed to a first level using a first set of program pulses within a first programming voltage range. A second memory cell to be programmed to a second level less than the first level is inhibited while programming the first memory cell to the first level. After programming the first memory cell to the first level, the second memory cell is programmed to the second level using a second set of program pulses within a second programming voltage range, where the first programming voltage range overlaps the second programming voltage range. The first memory cell that is programmed to the first level is inhibited while programming the second memory cell to the second level.

Claims (101)

1. A method of programming a memory, comprising:

programming a first memory cell to a first level using a first set of program pulses within a first programming voltage range;

inhibiting a second memory cell to be programmed to a second level less than the first level while programming the first memory cell to the first level;

after programming the first memory cell to the first level, programming the second memory cell to the second level using a second set of program pulses within a second programming voltage range; and

inhibiting the first memory cell that is programmed to the first level while programming the second memory cell to the second level;

wherein the first programming voltage range overlaps the second programming voltage range.

2. The method of claim 1 , wherein the first set of program pulses within the first programming voltage range is applied to the second memory cell while the second memory cell is inhibited while programming the first memory cell to the first level using the first set of program pulses within the first programming voltage range, and wherein the second set of program pulses within the second programming voltage range is applied to the first memory cell while the first memory cell is inhibited while programming the second memory cell to the second level using the second set of program pulses within the second programming voltage range.

3. The method of claim 1 , further comprising, while programming the first memory cell to the first level using the first set of program pulses, programming a third memory cell to a third level greater than the first level using the first set of program pulses.

4. The method of claim 3 , wherein the first, second, and third memory cells are in a same page of memory cells.

5. The method of claim 1 , wherein the first programming voltage range comprises a start programming voltage that is greater than a start programming voltage of the second programming voltage range and that is less than a stop programming voltage of the second programming voltage range.

6. The method of claim 1 , wherein the first programming voltage range and the second programming voltage range overlap only at a program start voltage of the first programming voltage range and a program stop voltage of the second programming voltage range.

7. The method of claim 1 , wherein the first level is greater than or equal to a first particular level and the second level is less than or equal to a second particular level that is less than the first particular level.

8. A method of programming a memory, comprising:

loading data to be programmed to levels within a first plurality of levels that are greater than or equal to a particular level;

programming first memory cells to the levels within the first plurality of levels using a first set of program pulses having programming voltages within a first programming voltage range;

inhibiting programming of second memory cells to be programmed to levels within a second plurality of levels that are less than the particular level while programming the first memory cells to the levels within the first plurality of levels;

after programming the first memory cells to the levels within the first plurality of levels, loading data to be programmed to the levels within the second plurality of levels;

after programming the first memory cells to the levels within the first plurality of levels, programming the second memory cells to the levels within the second plurality of levels using a second set of program pulses having programming voltages within a second programming voltage range; and

inhibiting programming of the first memory cells that were programmed to the levels within the first plurality of levels while programming the second memory cells to the levels within the second plurality of levels;

wherein the first programming voltage range overlaps the second programming voltage range.

9. The method of claim 8 , wherein loading the data to be programmed to the levels within the first plurality of levels comprises loading the data to be programmed to the levels within the first plurality of levels into latches that correspond to the first memory cells.

10. The method of claim 9 , wherein inhibiting the programming of the first memory cells comprises re-loading the latches that correspond to the first memory cells with inhibit data.

11. The method of claim 8 , wherein inhibiting programming of second memory cells comprises loading inhibit data into latches that correspond to the second memory cells.

12. The method of claim 11 , wherein loading the data to be programmed to the levels within the second plurality of levels comprises re-loading the latches that correspond to the second memory cells with the data to be programmed to the levels within the second plurality of levels.

13. The method of claim 8 , wherein the first memory cells and the second memory cells are in a same page of memory cells.

14. The method of claim 8 , wherein the first programming voltage range comprises a start programming voltage that is within the second programming voltage range.

15. The method of claim 8 , wherein the particular level is a first particular level and wherein the second plurality of levels that are less than the first particular level comprises the second plurality of levels being less than or equal to a second particular level that is less than the first particular level.

16. The method of claim 8 , wherein programming the first memory cells to the levels within the first plurality of levels using the first set of program pulses having programming voltages within a first programming voltage range, comprises programming different first memory cells to different first levels within the first plurality of levels using the first set of program pulses.

17. A method of programming a memory, comprising:

setting a first start program voltage and a first stop program voltage;

loading data for cells to be programmed to a level greater than or equal to a first particular level with actual data to be programmed;

loading data for cells to be programmed to a level less than a second particular level with an inhibit level;

programming the cells to be programmed with program pulses in a first range from the first start program voltage to the first stop program voltage;

setting a second start program voltage and a second stop program voltage;

re-loading data for the cells to be programmed to the level greater than or equal to the first particular level with an inhibit level;

re-loading data for cells to be programmed to the level less than the second particular level with actual data to be programmed; and

programming the re-loaded cells to be programmed with program pulses in a second range from the second start program voltage to the second stop program voltage;

wherein the first range from the first start program voltage to the first stop program voltage overlaps the second range from the second start program voltage to the second stop program voltage.

18. A method of programming a memory, comprising:

setting a first start program voltage and a first stop program voltage;

loading data for cells to be programmed to a level greater than or equal to a first particular level with actual data to be programmed;

loading data for cells to be programmed to a level less than or equal to a second particular level with an inhibit level;

programming the cells to be programmed with program pulses in a first range from the first start program voltage to the first stop program voltage;

setting a second start program voltage and a second stop program voltage;

re-loading data for the cells to be programmed to the level greater than or equal to the first particular level with an inhibit level;

re-loading data for cells to be programmed to the level than or equal to the second particular level with actual data to be programmed; and

programming the re-loaded cells to be programmed with program pulses in a second range from the second start program voltage to the second stop program voltage;

wherein the first particular level is one level higher than the second particular level.

19. The method of programming a memory, comprising:

setting a first start program voltage and a first stop program voltage;

loading data for cells to be programmed to a level grater than or equal to a first particular level with actual data to be programmed;

loading data for cells to be programmed to a level less than the first particular level with an inhibit level;

programming the cells to be programmed with program pulses in a first range from the first start program voltage to the first stop program voltage;

setting a second start program voltage and a second stop program voltage;

re-loading data for cells to be programmed to a level greater than a second particular level with an inhibit level;

re-loading data for cells to be programmed to the level less than or equal to the second particular level with actual data to be programmed; and

programming the re-loaded cells to be programmed with program pulses in a second range from the second start program voltage to the second stop program voltage;

wherein the first particular level is two levels lower than the second particular level.

20. The method of claim 18 , wherein the first start program voltage is below a middle voltage of a total programming voltage range comprising a range between the second start program voltage and the first stop program voltage, the first particular level is level 8 , the second stop program voltage is above the middle voltage, and the second particular level is level 7 .

21. The method of claim 19 , wherein the first start program voltage and the second stop program voltage are each approximately a middle voltage of a total programming voltage range comprising a range between the second start program voltage and the first stop program voltage, the first particular level is level 7 , and the second particular level is level 9 .

22. A method of programming a memory, comprising;

setting a first start program voltage and a first stop program voltage;

loading data for cells to be programmed to a level greater than or equal to a first particular level with actual data to be programmed;

loading data for cells to be programmed to a level less than the first particular level with an inhibit level;

programming the cells to be programmed with program pulses in a first range from the first start program voltage to the first stop program voltage;

setting a second start program voltage and a second stop program voltage;

re-loading data for cells to be programmed to a level greater than a second particular level with an inhibit level;

re-loading data for cells to be programmed to a level less than or equal to the second particular level with actual data to be programmed; and

programming the re-loaded cells to be programmed with program pulses in a second range from the second start program voltage to the second stop program voltage;

wherein the first start program voltage is approximately 17.5 volts, the first stop program voltage is 24 volts, the first particular level is level 7 , the second start program voltage is 12 volts, the second stop program voltage is approximately 18.5 volts, and the second particular level is 7 .

23. A method of programming a memory, comprising:

setting a first start program voltage and a first stop program voltage;

loading data for cells to be programmed to a level greater than or equal to a first particular level with actual data to be programmed;

loading data for cells to be programmed to a level less than a second particular level with an inhibit level;

programming the cells to be programmed with program pulses in a first range from the first start program voltage to the first stop program voltage;

setting a second start program voltage and a second stop program voltage;

re-loading data for cells to be programmed to the level greater than or equal to the first particular level with an inhibit level;

re-loading data for cells to be programmed to the level less than the second particular level with actual data to be programmed; and

programming the re-loaded cells to be programmed with program pulses in a second range from the second start program voltage to the second stop program voltage; wherein the first range overlaps the second range by approximately 2 volts.

24. A method of programming a memory, comprising:

setting a first start program voltage and a first stop program voltage;

loading data for cells to be programmed to a level greater than or equal to a first particular level with actual data to be programmed;

loading data for cells to be programmed to a level less than a second particular level with an inhibit level;

programming the cells to be programmed with program pulses in a first range from the first start program voltage to the first stop program voltage;

setting a second start program voltage and a second stop program voltage;

re-loading data for cells to be programmed to the level greater than or equal to the first particular level with an inhibit level;

re-loading data for cells to be programmed to the level less than a second particular level with actual data to be programmed; and

programming the re-loaded cells to be programmed with program pulses in a second range from the second start program voltage to the second stop program voltage;

wherein the first range and the second range overlap only at the first program start voltage and the second program stop voltage.

25. The method of claim 17 , wherein the first particular level is equal to the second particular level.

26. A method, comprising:

setting a first start program voltage and a first stop program voltage;

loading data for cells to be programmed to a level greater than or equal to a first particular level with actual data to be programmed;

loading data for cells to be programmed to a level less than a second particular level with an inhibit level;

programming the cells to be programmed with program pulses in a first range from the first start program voltage to the first stop program voltage;

setting a second start program voltage and a second stop program voltage;

re-loading data for the cells to be programmed to the level greater than or equal to the first particular level with an inhibit level;

re-loading data for cells to be programmed to the level less than the second particular level with actual data to be programmed; and

programming the re-loaded cells to be programmed with program pulses in a second range from the second start program voltage to the second stop program voltage;

wherein the first start program voltage is equal to or lower than the second stop program voltage.

27. The method of claim 26 , wherein the first particular level is equal to the second particular level.

Assignments (8)
CONFIRMATORY LICENSE Recorded Oct 23, 2023
From: MICRON TECHNOLOGY, INC.
To: LODESTAR LICENSING GROUP LLC
Reel/Frame 065313/0151 →
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →