SERIAL PERIPHERAL INTERFACE HOST PORT
A serial peripheral interface (SPI) host port is disclosed that enables a host external to a processor to access the processor's memory-mapped resources using SPI memory command protocol. An exemplary processor can include a system interconnect connected to memory-mapped resources and a SPI host port connected to the system interconnect. The SPI host port is configured to use SPI memory command protocol to access memory-mapped resources of the processor for the host external to the processor.
1 . A processor comprising:
a system interconnect connected to memory-mapped resources; and
a serial peripheral interface (SPI) host port connected to the system interconnect, wherein the SPI host port is configured to use an SPI memory command protocol to access memory-mapped resources of the processor for a host external to the processor.
2 . The processor of claim 1 , wherein the SPI host port includes a system master interface connected to the system interconnect, wherein the system master interface is configured to access the memory-mapped resources across the system interconnect based on an instruction received from the host external to the processor.
3 . The processor of claim 1 , wherein the SPI host port is configured to interpret a payload of an SPI communication packet received from the host as an access instruction and perform an access operation based on the access instruction, wherein the SPI communication packet is based on the SPI memory command protocol.
4 . The processor of claim 1 , wherein the SPI host port includes a SPI host port ready line for asserting an SPI host port ready signal to the host when the SPI host port is ready to perform an access operation.
5 . The processor of claim 1 , wherein the SPI host port includes a SPI host port status register that includes a SPI host port status ready bit that indicates when the SPI host port is ready to perform an access operation.
6 . The processor of claim 1 , wherein the SPI host port status register includes an error condition bit that indicates an error condition.
7 . The processor of claim 1 , wherein the SPI host port includes a SPI host port interrupt request line for asserting a SPI host port interrupt request signal when the SPI host port detects an error condition.
8 . The processor of claim 7 , further comprising a system event controller, wherein the SPI host port interrupt request line is connected to the system event controller.
9 . The processor of claim 7 , wherein the SPI host port includes a SPI host port control register that includes an error condition mask bit for controlling assertion of the SPI host port interrupt request signal.
10 . The processor of claim 1 , wherein the SPI host port includes a SPI host port trigger out line for asserting a SPI host port trigger out signal when the SPI host port is ready to perform an access operation.
11 . The processor of claim 10 , further comprising a trigger routing unit, wherein the SPI host port trigger out line is connected to the trigger routing unit.
12 . The processor of claim 10 , wherein the SPI host port includes a SPI host port control register that includes a trigger mode bit for controlling a source for asserting the SPI host port trigger out signal.
13 . The processor of claim 1 , wherein the SPI memory command protocol is a SPI SRAM/Flash style protocol.
14 . A method to be performed by a serial peripheral interface (SPI) host port to facilitate access to memory-mapped resources of a processor, the method comprising:
receiving an SPI communication packet based on a SPI memory command protocol from a host external to the processor;
interpreting a payload of the SPI communication packet as an access instruction; and
performing an access operation based on the access instruction.
15 . The method of claim 14 , further comprising asserting an SPI host port ready signal to the host when the SPI host port is ready to perform the access operation.
16 . The method of claim 14 , further comprising asserting an SPI host port status ready bit when the SPI host port is ready to perform the access operation.
17 . The method of claim 14 , further comprising asserting a SPI host port interrupt request signal when the SPI host port detects an error condition.
18 . The method of claim 14 , further comprising asserting a SPI host port trigger out signal when the SPI host port is ready to perform the access operation.
19 . A serial peripheral interface (SPI) comprising:
a serial peripheral interface (SPI) host port configured to interpret a payload of an SPI communication packet based on an SPI memory command protocol received from a host external to a processor as an access instruction and access memory-mapped resources of the processor for the host based on the access instruction.
20 . The SPI of claim 19 , wherein the SPI host port includes:
a SPI host port ready line for asserting an SPI host port ready signal to the host when the SPI host port is ready to perform an access operation; and
a SPI host port status register that includes a SPI host port status ready bit that indicates when the SPI host port is ready to perform an access operation.