Output circuit for semiconductor device, semiconductor device having output circuit, and method of adjusting characteristics of output circuit
View Patent ↗To decrease the circuit scale necessary for the calibration of the output circuit and to decrease the time required for the calibration operation. The invention includes a first output buffer and a second output buffer that are connected to a data pin, and a calibration circuit that is connected to a calibration pin. The first output buffer and the second output buffer include plural unit buffers. The unit buffers have mutually the same circuit structures. With this arrangement, the impedances of the first output buffer and the second output buffer can be set in common, based on the calibration operation using the calibration circuit. Consequently, both the circuit scale necessary for the calibration operation and the time required for the calibration operation can be decreased.
1. An output circuit for a semiconductor device comprising:
a first unit buffer connected to a data terminal;
a first pre-stage circuit configured to control the first unit buffer;
a second unit buffer connected to the data terminal;
a third unit buffer connected to the data terminal;
a second pre-stage circuit configured to control the second and third unit buffers;
a fourth unit buffer connected to the data terminal;
a fifth unit buffer connected to the data terminal;
a sixth unit buffer connected to the data terminal; and
a third pre-stage circuit configured to control the fourth, fifth, and sixth unit buffers;
wherein each of the first, second, third, fourth, fifth, and sixth unit buffers are calibrated to substantially the same impedance value.
2. The output circuit as claimed in claim 1 , wherein each of the first, second, third, fourth, fifth, and sixth unit buffers comprises a first driving unit and a second driving unit.
3. The output circuit as claimed in claim 1 , wherein the first, second, and third unit buffers are part of a first output buffer circuit and the fourth, fifth, and sixth unit buffers are part of a second output buffer circuit.
4. The output circuit as claimed in claim 1 , further comprising a calibration circuit configured to supply an impedance control signal in common to the first, second, and third pre-stage circuits, wherein the first, second, third, fourth, fifth, and sixth unit buffers are calibrated based upon the impedance control signal.
5. The output circuit as claimed in claim 1 , wherein each of the first, second, third, fourth, fifth, and sixth unit buffers comprises:
a first plurality of transistors arranged in parallel between a first voltage supply line and a first resistor; and
a second plurality transistors arranged in parallel between a second voltage supply line and a second resistor;
wherein the first and second resistors are connected in series and a connection point between the first and second resistors is connected to the data terminal.
6. The output circuit as claimed in claim 5 , wherein each of the first plurality of transistors are of a first conductivity type and each of the second plurality of transistors are of a second conductivity type opposite the first conductivity type.
7. The output circuit as claimed in claim 6 , wherein the first plurality of transistors comprises PMOS transistors and the first voltage supply line supplies a first voltage, and
wherein the second plurality of transistors comprises NMOS transistors and the second voltage supply line supplies a second voltage less than the first voltage.
8. The output circuit as claimed in claim 5 , wherein the first and second resistors have substantially the same resistance.
9. The output circuit as claimed in claim 1 , further comprising an output control circuit configured to supply first, second, and third control signals to the first, second, and third pre-stage circuits, respectively.
10. An input/output (I/O) circuit for a semiconductor device comprising:
a first output buffer circuit comprising first, second, and third unit buffers connected in common to a data terminal;
a first pre-stage circuit configured to control the first unit buffer;
a second pre-stage circuit configured to control the second and third unit buffers;
a second output buffer circuit comprising fourth, fifth, and sixth unit buffers connected in common to the data terminal; and
a third pre-stage circuit configured to control the fourth, fifth, and sixth unit buffers;
wherein each of the first, second, third, fourth, fifth, and sixth unit buffers are calibrated to substantially the same impedance value.
11. The I/O circuit as claimed in claim 10 , wherein each of the first, second, third, fourth, fifth, and sixth unit buffers comprises a first driving unit and a second driving unit.
12. The I/O circuit as claimed in claim 10 , further comprising a calibration circuit configured to supply an impedance control signal in common to the first, second, and third pre-stage circuits, wherein the first, second, third, fourth, fifth, and sixth unit buffers are calibrated based upon the impedance control signal.
13. The I/O circuit as claimed in claim 10 , further comprising an output control circuit configured to supply first, second, and third control signals to the first, second, and third pre-stage circuits, respectively.
14. The I/O circuit as claimed in claim 10 , further comprising an input circuit connected to the data terminal and in common to each of the first, second, third, fourth, fifth, and sixth unit buffers.