Group III-V HEMT having a selectably floating substrate
View Patent ↗There are disclosed herein various implementations of a group III-V high electron mobility transistor (HEMT) having a selectably floating substrate. Such a group III-V HEMT is situated over a substrate, and includes a transistor configured to selectably couple the substrate to ground and to selectably decouple the substrate from ground. The transistor is configured to ground the substrate when the group III-V HEMT is in an off-state and to cause the substrate to float when the group III-V HEMT is in an on-state.
1. A group III-V high electron mobility transistor (HEMT) comprising:
a substrate;
said group III-V HEMT situated over said substrate;
a transistor configured to selectably couple said substrate to ground and to selectably decouple said substrate from ground;
wherein said transistor grounds said substrate when said group III-V HEMT is in an off-state and causes said substrate to float when said group III-V HEMT is in an on-state.
2. The group III-V HEMT of claim 1 , wherein said group III-V HEMT comprises an enhancement mode HEMT.
3. The group III-V HEMT of claim 1 , wherein a gate of said group III-V HEMT is electrically coupled to a gate of said transistor.
4. The group III-V HEMT of claim 1 , wherein said group III-V HEMT and said transistor are monolithically integrated on said substrate.
5. The group III-V HEMT of claim 1 , wherein a gate of said group III-V HEMT is electrically coupled to a gate of said transistor by a through-substrate via.
6. The group III-V HEMT of claim 1 , wherein said group III-V HEMT comprises a III-Nitride HEMT.
7. The group III-V HEMT of claim 1 , wherein said transistor comprises a group IV p-channel metal-oxide-semiconductor (PMOS) transistor.
8. The group III-V HEMT of claim 1 , wherein said transistor comprises a depletion mode group IV PMOS transistor.
9. The group III-V HEMT of claim 1 , wherein said transistor has a breakdown voltage greater than or approximately equal to a breakdown voltage of said group III-V HEMT.
10. The group III-V HEMT of claim 1 , wherein said transistor comprises a depletion mode p-channel double-diffused MOS (p-channel DMOS) transistor.
11. A III-Nitride high electron mobility transistor (HEMT) comprising:
a substrate;
said III-Nitride HEMT situated over said substrate;
a group IV p-channel metal oxide transistor (PMOS) configured to selectably couple said substrate to ground and to selectably decouple said substrate from ground;
said group IV PMOS transistor configured to ground said substrate when said III-Nitride HEMT is in an off-state and to cause said substrate to float when said III-Nitride HEMT is in an on-state.
12. The III-Nitride HEMT of claim 11 , wherein said III-Nitride HEMT comprises an enhancement mode HEMT.
13. The III-Nitride HEMT of claim 11 , wherein a gate of said III-Nitride HEMT is electrically coupled to a gate of said group IV PMOS transistor.
14. The III-Nitride HEMT of claim 11 , wherein said III-Nitride HEMT and said group IV PMOS transistor are monolithically integrated on said substrate.
15. The III-Nitride HEMT of claim 11 , wherein a gate of said III-Nitride HEMT is electrically coupled to a gate of said group IV PMOS transistor by a through-substrate via.
16. The III-Nitride HEMT of claim 11 , wherein said III-Nitride HEMT comprises a high voltage (HV) HEMT.
17. The III-Nitride HEMT of claim 11 , wherein said group IV PMOS transistor comprises a silicon PMOS transistor.
18. The III-Nitride HEMT of claim 11 , wherein said group IV PMOS transistor comprises a depletion mode transistor.
19. The III-Nitride HEMT of claim 11 , wherein said group IV PMOS transistor has a breakdown voltage greater than or approximately equal to a breakdown voltage of said III-Nitride HEMT.
20. The III-Nitride HEMT of claim 11 , wherein said group IV PMOS transistor comprises a depletion mode p-channel double-diffused MOS (p-channel DMOS) transistor.