Composite group III-V and group IV transistor having a switched substrate
View Patent ↗There are disclosed herein various implementations of a group III-V composite transistor having a switched substrate. Such a group III-V composite transistor includes a composite field-effect transistor (FET) including a depletion mode group III-V high electron mobility transistor (HEMT) situated over a substrate. The depletion mode group III-V HEMT is cascoded with an enhancement mode group IV FET to produce the composite FET. The group III-V composite transistor also includes a transistor configured to selectably couple the substrate of the depletion mode group III-V HEMT to ground and to selectably decouple the substrate from ground. That transistor is configured to ground the substrate when the depletion mode group III-V HEMT is in an off-state and to cause the substrate to float when the depletion mode group III-V HEMT is in an on-state.
1. A group III-V composite transistor comprising:
a composite field-effect transistor (FET) including a depletion mode group III-V high electron mobility transistor (HEMT) situated over a substrate;
said depletion mode group III-V HEMT being cascoded with an enhancement mode group IV FET to produce said composite FET;
a transistor configured to selectably couple said substrate of said depletion mode group III-V HEMT to ground and to selectably decouple said substrate from ground, a source of said transistor being directly connected to a gate of said depletion mode group III-V HEMT;
said transistor configured to ground said substrate when said depletion mode group HEMT is in an off-state and to cause said substrate to float when said depletion mode group III-V HEMT is in an on-state.
2. The group III-V composite transistor of claim 1 , wherein said depletion mode group III-V HEMT and said transistor are monolithically integrated on said substrate.
3. The group III-V composite transistor of claim 1 , wherein a gate of said depletion mode group III-V HEMT is electrically coupled to a source of said transistor by a through-substrate via.
4. The group III-V composite transistor of claim 1 , wherein said depletion mode group III-V HEMT comprises a high voltage (HV) HEMT.
5. The group III-V composite transistor of claim 1 , wherein said enhancement mode group IV FET comprises a low voltage (LV) FET.
6. The group III-V composite transistor of claim 1 , wherein said depletion mode group III-V HEMT comprises a III-Nitride HEMT.
7. The group III-V composite transistor of claim 1 , wherein said transistor comprises a group IV p-channel metal-oxide-semiconductor (PMOS) transistor.
8. The group III-V composite transistor of claim 1 , wherein said transistor comprises a depletion mode group IV PMOS transistor.
9. The group III-V composite transistor of claim 1 , wherein said transistor has a breakdown voltage greater than or approximately equal to a breakdown voltage of said depletion mode group III-V HEMT.
10. The group III-V composite transistor of claim 1 , wherein said transistor comprises a depletion mode p-channel double-diffused MOS (p-channel DMOS) transistor.
11. A III-Nitride composite transistor comprising:
a composite field-effect transistor (FET) including a depletion mode III-Nitride high electron mobility transistor (HEMT) situated over a substrate;
said depletion mode III-Nitrate HEMT being cascoded with an enhancement mode group IV FET to produce said composite FET;
a group IV p-channel metal-oxide-semiconductor (PMOS) transistor configured to selectably couple said substrate of said depletion mode III-Nitride HEMT to ground and to selectably decouple said substrate from ground;
said group IV PMOS transistor configured to ground said substrate when said depletion mode III-Nitride HEMT is in an off-state and to cause said substrate to float when said depletion mode III-Nitride HEMT is in an on-state.
12. The III-Nitride composite transistor of claim 11 , wherein a gate of said depletion mode III-Nitride HEMT is electrically coupled to a source of said group IV PMOS transistor.
13. The III-Nitride composite transistor of claim 11 , wherein said depletion mode III-Nitride HEMT and said group IV PMOS transistor are monolithically integrated on said substrate.
14. The III-Nitride composite transistor of claim 11 , wherein a gate of said depletion mode III-Nitride HEMT is electrically coupled to a source of said group IV PMOS transistor by a through-substrate via.
15. The III-Nitride composite transistor of claim 11 , wherein said depletion mode III-Nitride HEMT comprises a high voltage (HV) HEMT.
16. The III-Nitride composite transistor of claim 11 , wherein said enhancement mode group IV FET comprises a low voltage (LV) FET.
17. The III-Nitride composite transistor of claim 11 , wherein said group IV PMOS transistor comprises a depletion mode group IV PMOS transistor.
18. The III-Nitride composite transistor of claim 11 , wherein said group IV PMOS transistor has a breakdown voltage greater than or approximately equal to a breakdown voltage of said depletion mode III-Nitride HEMT.
19. The III-Nitride composite transistor of claim 11 , wherein said group IV PMOS transistor comprises a depletion mode p-channel double-diffused MOS (p-channel DMOS) transistor.