Methods for dry etching semiconductor devices
The present invention provides methods for etching semiconductor devices, such aluminum nitride resonators. The methods herein allow for devices having improved etch profiles, such that nearly vertical sidewalls can be obtained. In some examples, the method employs a dry etch step with a primary etchant gas that omits BCl 3 , a common additive.
1. A method for etching a semiconductor, the method comprising:
placing a patterned semiconductor into a plasma reactor, wherein the patterned semiconductor comprises a semiconductor material and a hard mask disposed directly or indirectly on a planar surface of the semiconductor material, and wherein the hard mask defines at least one trench pattern;
introducing a first supplementary gas into the plasma reactor for a first supplemental period, wherein the first supplementary gas comprises BCl 3 and wherein a duration of the first supplemental period is less than a duration of a primary etching period;
etching an exposed semiconductor material located in proximity to the trench pattern by introducing a primary etchant gas into the plasma reactor for the primary etching period, wherein the primary etchant gas comprises Cl 2 and does not include BCl 3 , thereby providing an etched semiconductor; and
introducing a second supplementary gas into the plasma reactor for a second supplemental period, wherein the second supplementary gas comprises BCl 3 and wherein a duration of the second supplemental period is less than a duration of the primary etching period.
2. The method of claim 1 , wherein the at least one trench pattern of the hard mask was etched by employing a plasma etch process.
3. The method of claim 1 , wherein the plasma reactor is an inductively coupled plasma reactor.
4. The method of claim 3 , wherein the inductively coupled plasma reactor is operated at a source power of from about 500 W to about 2000 W and at a bias of from about 40 W to about 200 W.
5. The method of claim 1 , wherein the plasma reactor is maintained at a low operating pressure less than about 25 mTorr.
6. The method of claim 1 , wherein the primary etchant gas consists essentially of Cl 2 .
7. The method of claim 1 , wherein the duration of the primary etching period is of from about 100 seconds to about 400 seconds.
8. The method of claim 1 , wherein the semiconductor material comprises a piezoelectric material selected from the group consisting of an aluminum nitride, a III-V material, lithium niobate, lithium tantalate, and doped forms thereof.
9. The method of claim 1 , wherein the patterned semiconductor comprises a semiconductor stack.
10. The method of claim 9 , wherein the semiconductor stack comprises a piezoelectric layer, a bottom electrode layer disposed beneath the piezoelectric layer, and an insulator layer disposed between the bottom electrode layer and a substrate.
11. The method of claim 10 , wherein the substrate further comprises a release layer.
12. The method of claim 1 , wherein a vertical sidewall of the etched semiconductor has a sidewall angle greater than about 80°.
13. The method of claim 1 , wherein the duration of the first supplemental period is from about 5 seconds to about 50 seconds, and wherein the duration of the primary etching period is from about 100 seconds to about 400 seconds.
14. The method of claim 1 , wherein the duration of the second supplemental period is from about 5 seconds to about 50 seconds, and wherein the duration of the primary etching period is from about 100 seconds to about 400 seconds.
15. The method of claim 1 , further comprising, after the etching step:
removing the hard mask by employing a selective anisotropic oxide etch.
16. The method of claim 15 , further comprising, after the removing step:
releasing a portion of the etched semiconductor, thereby providing a released resonator portion.
17. The method of claim 16 , wherein the patterned semiconductor comprises a semiconductor stack comprising a release layer, and wherein the releasing step comprises etching the release layer.
18. A method for etching a semiconductor, the method comprising:
placing a patterned semiconductor into a plasma reactor, wherein the patterned semiconductor comprises a semiconductor material and a hard mask disposed directly or indirectly on a planar surface of the semiconductor material, and wherein the hard mask defines at least one trench pattern;
introducing a first supplementary gas into the plasma reactor for a first supplemental period, wherein the first supplementary gas comprises BCl 3 ;
etching an exposed semiconductor material located in proximity to the trench pattern by introducing a primary etchant gas into the plasma reactor for a primary etching period, wherein the primary etchant gas comprises Cl 2 and does not include BCl 3 ;
introducing a second supplementary gas into the plasma reactor for a second supplemental period, wherein the second supplementary gas comprises BCl 3 ; and
removing the hard mask by employing a selective anisotropic oxide etch, thereby providing an etched semiconductor,
wherein a duration of each of the first and the second supplemental periods is, independently, less than a duration of the primary etching period.
19. The method of claim 18 , wherein the duration of each of the first and second supplemental period is from about 5 second to about 50 seconds; and wherein the duration of the primary etching period is from about 100 seconds to about 400 seconds.
20. A method for fabricating a semiconductor resonator, the method comprising:
placing a patterned semiconductor into a plasma reactor, wherein the patterned semiconductor comprises a piezoelectric material and a hard mask disposed directly or indirectly on a planar surface of the piezoelectric material, and wherein the hard mask defines at least one trench pattern that provides a first dimension of a resonator portion;
introducing a first supplementary gas into the plasma reactor for a first supplemental period, wherein the first supplementary gas comprises BCl 3 ;
etching an exposed semiconductor material located in proximity to the trench pattern by introducing a primary etchant gas into the plasma reactor for a primary etching period, wherein the primary etchant gas comprises Cl 2 and does not include BCl 3 , thereby defining at least one dimension of the resonator portion;
introducing a second supplementary gas into the plasma reactor for a second supplemental period, wherein the second supplementary gas comprises BCl 3 ;
removing the hard mask by employing a selective anisotropic oxide etch; and
releasing a portion of the etched semiconductor, thereby defining a second dimension of the resonator portion and providing the semiconductor resonator,
wherein a duration of each of the first and the second supplemental periods is, independently, less than a duration of the primary etching period.
21. The method of claim 20 , wherein the piezoelectric material comprises an aluminum nitride, a III-V material, lithium niobate, lithium tantalate, and doped forms thereof; and wherein a vertical sidewall of the semiconductor resonator has a sidewall angle greater than about 80°.
22. The method of claim 20 , wherein the duration of each of the first and second supplemental period is from about 5 second to about 50 seconds; and wherein the duration of the primary etching period is from about 100 seconds to about 400 seconds.