Thin film transistor array substrate, display panel and display device
View Patent ↗A thin film transistor array substrate for a display device generally includes: a substrate; a plurality of gate lines and a plurality of data lines arranged on the substrate intersecting with and insulated from each other; and a plurality of pixel elements arranged in areas defined by the gate lines and the data lines. At least one of the pixel elements includes: a switch element; an insulation layer located on the switch element; and a pixel electrode located at the insulation layer. The insulation layers of the pixel elements define a plurality of vias. The pixel electrodes of two adjacent pixel elements are electrically coupled with the corresponding switch elements of the two adjacent pixel elements through a common via defined by the insulation layers of the two adjacent pixel elements. The two adjacent pixel elements are disposed along extensions of the plurality of the gate lines.
1. A thin film transistor array substrate for a display device, the array substrate comprising:
a substrate;
a plurality of gate lines disposed on the substrate;
a plurality of data lines disposed on the substrate, wherein the plurality of the gate lines and the plurality of the data lines intersect with each other to define a plurality of areas and are insulated from each other; and
a plurality of pixel elements disposed in the plurality of the areas defined by the plurality of the gate lines and the plurality of the data lines, at least one of the pixel elements comprising:
a switch element;
an insulation layer located on the switch element; and
a pixel electrode located at the insulation layer;
wherein insulation layers of the plurality of the pixel elements define a plurality of vias, the pixel electrodes of two adjacent pixel elements are electrically coupled with the corresponding switch elements of the two adjacent pixel elements through one common via defined by the insulation layers, the two adjacent pixel elements are disposed along extensions of the plurality of the gate lines;
the plurality of the vias each define a width dimension W along the extensions of the plurality of the gate lines, the plurality of the pixel elements each define a width dimension L along the extensions of the plurality of the gate lines, and W≦2L−15 μm; and
the plurality of pixel elements define a plurality of rows of the pixels elements arranged along the extensions of the plurality of the gate lines and a plurality of columns of the pixel elements arranged along extensions of the plurality of the data lines,
in the M-th row of the plurality of rows of the pixel elements, one of the plurality of the vias is shared by a pixel element in the N-th column and a pixel element in the adjacent (N+1)-th column, M and N are natural numbers; and
in the (M+1)-th row of the plurality of rows of the pixel elements, one of the plurality of the vias is shared by a pixel element in the (N+1)-th column and a pixel element in the adjacent (N+2)-th column.
2. The array substrate of claim 1 , wherein the array substrate further comprises a plurality of spacers each located between two adjacent vias of the plurality of vias along the extensions of the plurality of the gate lines.
3. A display panel, comprising a thin film transistor array substrate, wherein the thin film transistor array substrate comprises:
a substrate;
a plurality of gate lines disposed on the substrate;
a plurality of data lines disposed on the substrate, wherein the plurality of the gate lines and the plurality of the data lines intersect with each other to define a plurality of areas and are insulated from each other; and a plurality of pixel elements arranged in the plurality of the areas defined by the plurality of the gate lines and the plurality of the data lines, at least one of the pixel elements comprising:
a switch element;
an insulation layer located on the switch element; and
a pixel electrode located at the insulation layer;
wherein insulation layers of the plurality of the pixel elements define a plurality of vias, the pixel electrodes of two adjacent pixel elements are electrically coupled with the corresponding switch elements of the two adjacent pixel elements through one common via defined by the insulation layers, the two adjacent pixel elements are disposed along extensions of the plurality of the gate lines;
the plurality of the vias each define a width dimension W along the extensions of the plurality of the gate lines, the plurality of the pixel elements each define a width dimension L along the extensions of the plurality of the gate lines, and W≦2L−15 μm; and
the plurality of pixel elements define a plurality of rows of the pixels elements arranged along the extensions of the plurality of the gate lines and a plurality of columns of the pixel elements arranged along extensions of the plurality of the data lines,
in the M-th row of the plurality of rows of the pixel elements, one of the plurality of the vias is shared by a pixel element in the N-th column and a pixel element in the adjacent (N+1)-th column, M and N are natural numbers; and
in the (M+1)-th row of the plurality of rows of the pixel elements, one of the plurality of the vias is shared by a pixel element in the (N+1)-th column and a pixel element in the adjacent (N+2)-th column.
4. The display panel of claim 3 , wherein the thin film transistor array substrate further comprises an active layer of one of amorphous silicon or low temperature poly-silicon or oxide.