Semiconductor device
According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.
1. A semiconductor device comprising:
first to n-th (n is an integer of 2 or more) nonvolatile semiconductor memories;
(n+1)-th to 2n-th nonvolatile semiconductor memories;
first to n-th resistive elements;
a controller configured to control the first to 2n-th nonvolatile semiconductor memories;
first to n-th signal lines respectively connecting the controller and the first to n-th resistive elements;
(n+1)-th to 2n-th signal lines respectively connecting the first to n-th resistive elements and the first to n-th nonvolatile semiconductor memories;
(2n+1)-th to 3n-th signal lines divided from the (n+1)-th to 2n-th signal lines, and respectively connected with the (n+1)-th to 2n-th nonvolatile semiconductor memories; and
a substrate, wherein
the substrate includes
a front surface layer including a wiring pattern formed on a front surface of the substrate, and on which the first to n-th nonvolatile semiconductor memories, the first to n-th resistive elements, and the controller are mounted,
a rear surface layer including a wiring pattern formed on a rear surface of the substrate, and on which the (n+1)-th to 2n-th nonvolatile semiconductor memories are mounted, and
a connector configured to be connected with an external device, and
the first to n-th nonvolatile semiconductor memories and the (n+1)-th to 2n-th nonvolatile semiconductor memories are symmetrically disposed with respect to the substrate.
2. The semiconductor device according to claim 1 , wherein n is 4.
3. The semiconductor device according to claim 2 , further comprising:
a temperature sensor mounted on the front surface layer.
4. The semiconductor device according to claim 2 , further comprising:
an internal wiring layer provided between the front surface layer and the rear surface layer, and including a wiring pattern, wherein
each of the (2n+1)-th to 3n-th signal lines includes a portion passing through the internal wiring layer.
5. The semiconductor device according to claim 2 , wherein
the k-th (k is an integer that satisfies 1≦k≦2n) nonvolatile semiconductor memory determines whether to operate in response to a signal from the (n+k)-th signal line, on a basis of a channel enable signal of the k-th nonvolatile semiconductor memory.
6. The semiconductor device according to claim 2 , wherein
two nonvolatile semiconductor memories symmetrically disposed with respect to the substrate, of the first to 2n-th nonvolatile semiconductor memories, are configured to be individually operable, on a basis of whether respective channel enable signals of these two nonvolatile semiconductor memories are active or not.
7. The semiconductor device according to claim 2 , wherein
the substrate includes a long side and a short side perpendicular to the long side in plan view,
the connector is provided on the short side of the substrate, and
the first to n-th nonvolatile semiconductor memories are provided on the opposite side to the connector as viewed from a position of the controller in plan view.
8. The semiconductor device according to claim 7 , further comprising:
a volatile semiconductor memory provided on the same side as the connector as viewed from the first to n-th nonvolatile semiconductor memories in plan view.
9. The semiconductor device according to claim 1 , wherein
the substrate includes a long side and a short side perpendicular to the long side in plan view,
the connector is provided on the short side of the substrate, and
the first to n-th nonvolatile semiconductor memories are provided on the opposite side to the connector as viewed from a position of the controller in plan view.
10. The semiconductor device according to claim 9 , further comprising:
a volatile semiconductor memory provided on the same side as the connector as viewed from the first to n-th nonvolatile semiconductor memories in plan view.
11. The semiconductor device according to claim 9 , further comprising:
an internal wiring layer provided between the front surface layer and the rear surface layer, and including a wiring pattern, wherein
each of the (2n+1)-th to 3n-th signal lines includes a portion passing through the internal wiring layer.
12. The semiconductor device according to claim 9 , wherein
the k-th (k is an integer that satisfies 1 ≦k≦2n) nonvolatile semiconductor memory determines whether to operate in response to a signal from the (n +k)-th signal line, on a basis of a channel enable signal of the k-th nonvolatile semiconductor memory.
13. The semiconductor device according to claim 9 , wherein
two nonvolatile semiconductor memories symmetrically disposed with respect to the substrate, of the first to 2n-th nonvolatile semiconductor memories, are configured to be individually operable, on a basis of whether respective channel enable signals of these two nonvolatile semiconductor memories are active or not.
14. The semiconductor device according to claim 9 , wherein
the n is an even number, and first to n/2-th nonvolatile semiconductor memories, of the first to n-th nonvolatile semiconductor memories, are disposed on one long side of the substrate, and (n/2+1)-th to n-th nonvolatile semiconductor memories are disposed on the other long side of the substrate.
15. The semiconductor device according to claim 14 , comprising:
wiring lines respectively connecting the first to n-th nonvolatile semiconductor memories, and the controller, wherein
a ratio of the shortest wiring line to the longest wiring line is approximately 1:2.
16. The semiconductor device according to claim 1 , further comprising:
a temperature sensor mounted on the front surface layer.
17. The semiconductor device according to claim 1 , further comprising:
an internal wiring layer provided between the front surface layer and the rear surface layer, and including a wiring pattern, wherein
each of the (2n+1)-th to 3n-th signal lines includes a portion passing through the internal wiring layer.
18. The semiconductor device according to claim 1 , wherein
the k-th (k is an integer that satisfies 1≦k≦2n) nonvolatile semiconductor memory determines whether to operate in response to a signal from the (n+k)-th signal line, on a basis of a channel enable signal of the k-th nonvolatile semiconductor memory.
19. The semiconductor device according to claim 1 , wherein
two nonvolatile semiconductor memories symmetrically disposed with respect to the substrate, of the first to 2n-th nonvolatile semiconductor memories, are configured to be individually operable, on a basis of whether respective channel enable signals of these two nonvolatile semiconductor memories are active or not.
20. The semiconductor device according to claim 1 , wherein
the nonvolatile semiconductor memories are NAND flash memories.