IP Library › Granted Patent US 9,274,829
Granted Patent B2
US 9,274,829 · App. 14/731,753 · Granted Mar 1, 2016

Handling interrupt actions for inter-thread communication

Inventors: Andrew J. Declercq (Austin, TX); Ahmed Gheith (Austin, TX); Aditya Kumar (Austin, TX)
Assignee: International Business Machines Corporation
G06F9/4812G06F9/52G06F9/542
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Quick Facts
Patent No.
US 9,274,829
App. No.
14/731,753
Filed
Jun 5, 2015
Granted
Mar 1, 2016
Kind
B2
Examiner
ZHAO, BING
Art Unit
2195
USPC
718/107
Abstract

A mechanism is provided for handling interrupt actions for inter-thread communication. In association with a first processor thread, a thread action data structure is provided that comprises a non-blocking synchronization data structure and an internal list data structure of pending interrupts having no form of synchronization. A post of an interrupt action is received from a second processor thread to the thread action data structure associated with the first processor thread, where the interrupt action is added to the non-blocking synchronization data structure of the thread action data structure. The interrupt action is moved from the non-blocking synchronization data structure to the internal list data structure of pending interrupts for handling by the first processor thread. The internal list data structure of pending interrupts is processed to thereby handle interrupt actions moved to the internal list data structure.

Claims (19)

1. A method, in a data processing system comprising a processor and a memory, for handling interrupt actions for inter-thread communication, the method comprising:

providing, by the data processing system, in association with a first processor thread, a thread action data structure comprising a non-blocking synchronization data structure and an internal list data structure of pending interrupts, wherein the thread action data structure associated with the first processor thread receives interrupts from other processor threads in the computing device;

receiving, by the data processing system, a post of an interrupt action from a second processor thread to the thread action data structure associated with the first processor thread, wherein the interrupt action is added to the non-blocking synchronization data structure of the thread action data structure;

moving, by the data processing system, the interrupt action from the non-blocking synchronization data structure to the internal list data structure of pending interrupts for handling by the first processor thread, wherein, responsive to receiving a post of a new interrupt action while the interrupt action is being moved from the non-blocking synchronization data structure to the internal list data structure of pending interrupt, the method further comprises:

delaying, by the data processing system, the posting of the new interrupt action to the non-blocking synchronization data structure until after the interrupt action is moved from the non-blocking synchronization data structure to the internal list data structure of pending interrupts;

responsive to the interrupt action being moved from the non-blocking synchronization data structure to the internal list data structure of pending interrupts, adding, by the data processing system, the new interrupt action to the non-blocking synchronization data structure of the thread action data structure; and

updating, by the data processing system, an atomic reference to a head of the non-blocking synchronization data structure in response adding the new interrupt action from the second processor thread to the thread action data structure associated with the first processor thread, wherein the atomic reference to the head of the non-blocking synchronization data structure points to the new interrupt action in the non-blocking synchronization data structure; and

processing, by the data processing system, the internal list data structure of pending interrupts to thereby handle interrupt actions moved to the internal list data structure.

2. The method of claim 1 , wherein moving the interrupt action from the non-blocking synchronization data structure to the internal list data structure of pending interrupts for handling by the first processor thread further comprises:

advancing, by the data processing system, an atomic reference to a next most recently posted interrupt action in the non-blocking synchronization data structure in response to moving the interrupt action from the non-blocking synchronization data structure to the internal list data structure of pending interrupts for handling by the first processor thread.

3. The method of claim 1 , further comprising:

blocking, by the data processing system, posting of interrupt actions by other threads to the non-blocking synchronization data structure while the interrupt action is being moved from the non-blocking synchronization data structure to the internal list data structure of pending interrupts.

4. The method of claim 1 , further comprising:

updating, by the data processing system, the atomic reference to the head of the non-blocking synchronization data structure in response to receiving the post of the interrupt action from the second processor thread to the thread action data structure associated with the first processor thread, wherein the atomic reference points to the interrupt action from the second processor thread in the non-blocking synchronization data structure.

5. The method of claim 1 , further comprising:

periodically checking, by the data processing system, the atomic reference to the head of the non-blocking synchronization data structure to determine whether there are any pending interrupt actions in the non-blocking synchronization data structure; and

responsive to determining that there are pending interrupt actions in the non-blocking synchronization data structure based on results of checking the atomic reference to the head, moving, by the data processing system, the interrupt action from the non-blocking synchronization data structure to the internal list data structure of pending interrupts for handling by the first processor thread.

6. The method of claim 1 , further comprising:

providing, by the data processing system, in association with all processor threads in the data processing system, a respective thread action data structure comprising a respective non-blocking synchronization data structure and a respective internal list data structure of pending interrupts.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 5, 2015
From: DECLERCQ, ANDREW J.; GHEITH, AHMED; KUMAR, ADITYA
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 035835/0419 →
Continuity (2)
Continuation 14030366 · Sep 18, 2013
Related Publication 20150268988A1 · Sep 24, 2015