Apparatuses and methods for providing set and reset voltages at the same time
Apparatuses and methods are described, such as those involving driver circuits that are configured to provide reset and set voltages to different variable state material memory cells in an array at the same time. Additional apparatuses, and methods are described.
1. A memory device, comprising:
an array of memory cells arranged in rows and columns, each of the cells including a variable state material; and
a driver coupled to the array of memory cells to provide three different voltages to different memory cells in the array at the same time, the three different voltages including set and reset voltages.
2. The memory device of claim 1 , wherein the variable state material includes a resistance switching material.
3. The memory device of claim 1 , wherein the array further includes selector devices to access memory cells.
4. The memory device of claim 3 , wherein the selector devices include N channel transistors.
5. The memory device of claim 3 , wherein the selector devices include P channel transistors.
6. A memory device, comprising:
an array of memory cells arranged in rows and columns, each of the cells including a variable state material; and
a driver coupled to the array of memory cells to provide set, reset, and inhibit voltages to different columns in the array at the same time.
7. The memory device of claim 6 , wherein the set voltage is configured to operate at approximately 4 volts.
8. The memory device of claim 6 , wherein the reset voltage is configured to operate at approximately 2 volts.
9. The memory device of claim 6 , wherein the inhibit voltage is configured to operate at approximately 3 volts.
10. An information handling system, comprising:
an array of memory cells arranged in rows and columns, each of the cells including a variable state material; and
a driver coupled to the array of memory cells to provide three different voltages to different columns in the array at the same time, the three different voltages including set and reset voltages; and
a host processor coupled to the driver.
11. The information handling system of claim 10 , wherein the host processor and the array of memory cells are located in a single chip assembly.
12. The information handling system of claim 10 , wherein the driver is further configured to provide an inhibit voltage to different columns in the array at the same time as set and reset voltages.
13. The information handling system of claim 10 , wherein the variable state material includes a resistance switching material.