Methods and circuits for asymmetric distribution of channel equalization between devices
A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.
1. A method for obtaining a pre-cursor intersymbol interference (ISI) coefficient, the method comprising:
sampling a signal with reference to a data-level voltage to recover sampled bit patterns, the signal exhibiting post-cursor ISI and pre-cursor ISI;
while measuring an error rate of a first of the bit patterns, adjusting the data-level voltage to achieve a first error-rate value and recording the adjusted data-level voltage as a first data-level voltage;
while measuring an error rate of a second of the bit patterns, adjusting the data-level voltage to achieve a second error-rate value and recording the adjusted data-level voltage as a second data-level voltage; and
calculating the pre-cursor ISI coefficient using the first data-level voltage and the second data-level voltage.
2. The method of claim 1 , wherein measuring the error rate of a first of the bit patterns comprising setting a data filter to sense the first of the bit patterns in an incoming signal.
3. The method of claim 1 , wherein the first of the bit patterns differs from the second of the bit patterns by a single bit.
4. The method of claim 1 , wherein the first error-rate value and the second error-rate value are equal.
5. The method of claim 1 , wherein the first error-rate value is 50%.
6. The method of claim 1 , further comprising deriving a post-cursor ISI coefficient and holding the post-cursor ISI coefficient constant while measuring the error rate of at least one of the first and second of the bit patterns.
7. The method of claim 1 , further comprising holding the calculated pre-cursor ISI coefficient constant and calculating a second pre-cursor ISI coefficient while sampling a second signal.
8. The method of claim 1 , further comprising deriving a transmit coefficient from the calculated pre-cursor ISI coefficient.
9. An integrated circuit comprising:
a receiver pad to receive an incoming data signal;
a data sampler coupled to the receiver pad to sample the data signal, the data sampler to produce data samples;
a signal monitor coupled to the receiver pad to sample the data signal with reference to data-level voltage, the signal monitor to produce error samples; and
an equalization-control circuit coupled to the signal monitor, the equalization-control circuit to generate a pre-cursor intersymbol interference (ISI) coefficient from the error samples.
10. The integrated circuit of claim 9 , the equalization-control circuit coupled to the data sampler to generate the pre-cursor ISI coefficient from the error samples and the data samples.
11. The integrated circuit of claim 9 , wherein the equalization-control circuit adjusts the data-level voltage to achieve a first error-rate value while measuring an error rate of a first bit pattern, adjusts the data-level voltage to achieve a second error-rate value while measuring an error rate of a second bit pattern, and calculates the pre-cursor ISI coefficient using the data-level voltages that achieve the first and second error-rate values.
12. The integrated circuit of claim 9 , further comprising a transmitter coupled to the equalization-control circuit, the transmitter including a precursor tap to receive the pre-cursor ISI coefficient.
13. The integrated circuit of claim 12 , further comprising an equalizer coupled to the receiver pad, the equalizer to apply a receiver post-cursor ISI coefficient to the incoming data signal.
14. The integrated circuit of claim 13 , wherein the equalization-control circuit holds the receiver post-cursor ISI coefficient constant while adjusting the data-level voltage to calculate the pre-cursor ISI coefficient.
15. The integrated circuit of claim 13 , wherein the transmitter includes a post-cursor tap.
16. The integrated circuit of claim 15 , wherein the equalization-control circuit derives a transmit post-cursor ISI coefficient from the receiver post-cursor ISI coefficient and applies the transmit post-cursor ISI coefficient to the post-cursor tap of the transmitter.
17. An integrated circuit, comprising:
a transmitter to transmit a first data signal, the transmitter including a transmit equalizer with a pre-cursor tap;
a receiver to receive a second data signal, the receiver including a receive equalizer with a post-cursor tap; and
an equalization control circuit coupled to the transmit equalizer and the receive equalizer, the equalization control circuit including:
means for generating a post-cursor equalization coefficient and conveying the post-cursor equalization coefficient to the post-cursor tap; and
means for deriving a pre-cursor equalization coefficient from the second data signal and conveying the pre-cursor equalization coefficient to the pre-cursor tap.
18. The integrated circuit of claim 17 , wherein the means for deriving the pre-cursor equalization coefficient from the second data signal derives the pre-cursor equalization coefficient from the post-cursor equalization coefficient.
19. The integrated circuit of claim 17 , the receiver further including means for sampling the second data signal and means for monitoring the second data signal for errors.
20. The integrated circuit of claim 19 , wherein the equalization control circuit generates the pre-cursor equalization coefficient using the sampled second data signal and the errors.