METHOD FOR IMPROVING SAFETY OF VOLTAGE REGULATOR
A method for improving safety of voltage regulator is disclosed. In order to improve safety of a voltage regulator, a MOS-FET is disposed on a source power lane that receives power supplied from a DC power supply. A set of voltage regulators is connected to a set of fork power lanes, correspondingly, branching off from the source power lane. PTC thermistors are disposed on a surface or in the vicinity of semiconductor chips of the voltage regulators. When temperature at any one of the PTC thermistors increases, a protection controller turns off the MOS-FET. When temperature detected by a temperature sensor incorporated within the semiconductor chip has increased, each of the voltage regulators turns off the MOS-FET via a base management controller.
1 . A power-supply system comprising:
a protection switch disposed on a power lane receiving power from a DC power supply;
a plurality of voltage regulators, wherein at least one of said voltage regulators includes a switching element and branching off from said power lane;
a temperature sensor for detecting temperature of said voltage regulators; and
a controller for turning off said protection switch when temperature at any one of said voltage regulators has increased and for stopping power supplied to said plurality of voltage regulators.
2 . The power-supply system of claim 1 , wherein said temperature sensor detects temperature of a semiconductor chip when said switching element is incorporated within said semiconductor chip.
3 . The power-supply system of claim 2 , wherein said temperature sensor detects temperatures inside of said semiconductor chip.
4 . The power-supply system of claim 1 , wherein said temperature sensor includes a FTC thermistor.
5 . The power-supply system of claim 1 , wherein in response to an abnormality for ON/OFF resistances of said switching elements, said voltage regulators send a signal to turn off said protection switch to said controller.
6 . The power-supply system of claim 1 , wherein said voltage regulators include a first voltage regulator and a second voltage regulator that output mutually different voltages, and loads of said voltage regulators include a device that operates with output voltage from said first voltage regulator and output voltage from said second voltage regulator.
7 . A sub-system for a computer comprising:
a processor and a system memory;
a protection switch disposed on a power lane receiving power from a DC power supply;
a plurality of voltage regulators, wherein at least one of said voltage regulators includes a switching element to supply power to said processor and said system memory;
a first temperature sensor for detecting temperature of said voltage regulators; and
a first protection circuit for turning off said protection switch in response to a temperature at any of said voltage regulators has increased.
8 . The sub-system of claim 7 , wherein said switching element is incorporated within a semiconductor chip, and said first protection circuit turns off said protection switch in response to a temperature of said semiconductor chip has increased.
9 . The sub-system of claim 8 , further comprising:
a second temperature sensor incorporated within said semiconductor chip; and
a second protection circuit for turning off said protection switch in response to a temperature detected by said second temperature sensor has increased.
10 . A method for improving safety of a voltage regulator, said method comprising:
providing a voltage regulator with a switching element at one of a plurality of fork power lanes branching off from a source power lane;
detecting temperature at said switching element of one of said voltage regulators; and
stopping power supplied from said source power lane in response to a temperature at any of said voltage regulators has increased.
11 . The method of claim 10 , wherein said detecting temperature further includes detecting temperature of a semiconductor chip when said switching element is incorporated within said semiconductor chip.
12 . The method of claim 10 , further comprising: in response to an abnormality occurs in ON resistance of said switching elements, stopping power supplied from said source power lane.
13 . The method of claim 10 , further comprising: in response to an abnormality occurs in OFF resistance of said switching elements, stopping power supplied from said source power lane.