Semiconductor package
A semiconductor package includes a support substrate; a stress relaxation layer provided on a main surface of the support substrate; a semiconductor device located on the stress relaxation layer; an encapsulation material covering the semiconductor device, the encapsulation material being formed of an insulating material different from that of the stress relaxation layer; a line running through the encapsulation material and electrically connected to the semiconductor device; and an external terminal electrically connected to the line. Where the support substrate has an elastic modulus of A, the stress relaxation layer has an elastic modulus of B, and the encapsulation material has an elastic modulus of C under a same temperature condition, the relationship of A>C>B or C>A>B is obtained.
1. A semiconductor package, comprising:
a support substrate;
a stress relaxation layer provided on and in contact with a main surface of the support substrate;
a semiconductor device located on the stress relaxation layer;
an encapsulation material covering the semiconductor device, the encapsulation material being formed of an insulating material different from that of the stress relaxation layer;
a line layer arranged on the encapsulation material and electrically connected to the semiconductor device via an opening in the encapsulation material; and
an external terminal electrically connected to the line layer.
2. A semiconductor package, comprising:
a support substrate;
a stress relaxation layer provided on and in contact with a main surface of the support substrate;
a semiconductor device located on the stress relaxation layer;
an encapsulation material covering the semiconductor device, the encapsulation material being formed of an insulating material different from that of the stress relaxation layer;
a line layer arranged on the encapsulation material and electrically connected to the semiconductor device via an opening in the encapsulation material; and
an external terminal electrically connected to the line layer,
wherein the stress relaxation layer is provided with an opening formed in the vicinity of the semiconductor device.
3. The semiconductor package according to claim 2 , wherein the opening is an alignment mark, and has a polygonal shape having a side of a length of 480 μm or less or a circular shape having a diameter of 480 μm or less.
4. A semiconductor package, comprising:
a support substrate;
a stress relaxation layer provided on and in contact with a main surface of the support substrate;
a conductive layer provided on the stress relaxation layer;
a semiconductor device located on the conductive layer;
an encapsulation material covering the semiconductor device, the encapsulation material being formed of an insulating material different from that of the stress relaxation layer;
a line layer arranged on the encapsulation material and electrically connected to the semiconductor device via an opening in the encapsulation material; and
an external terminal electrically connected to the line layer.
5. The semiconductor package according to claim 4 , wherein the conductive a er forms at least one of a capacitor, a resistor and an inductor.
6. A semiconductor package, comprising:
a support substrate;
a stress relaxation layer provided on and in contact with a main surface of the support substrate;
a conductive layer provided on the stress relaxation layer;
a semiconductor device located on the conductive layer;
an encapsulation material covering the semiconductor device, the encapsulation material being formed of an insulating material different from that of the stress relaxation layer;
a line layer arranged on the encapsulation material and electrically connected to the semiconductor device via an opening in the encapsulation material; and
an external terminal electrically connected to the line layer,
wherein the stress relaxation layer is provided with an opening formed in the vicinity of the semiconductor device.
7. The semiconductor package according to claim 6 , wherein the opening is an alignment mark, and has a polygonal shape having a side of a length of 480 μm or less or a circular shape having a diameter of 480 μm or less.
8. A semiconductor package, comprising:
a support substrate;
a stress relaxation layer provided on and in contact with a main surface of the support substrate;
a conductive layer provided on the stress relaxation layer;
a semiconductor device surrounded by the conductive layer and located on the stress relaxation layer;
an encapsulation material covering the semiconductor device, the encapsulation material being formed of an insulating material different from that of the stress relaxation layer;
a line layer arranged on the encapsulation material and electrically connected to the semiconductor device via an opening in the encapsulation material; and
an external terminal electrically connected to the line layer.
9. The semiconductor package according to claim 8 , wherein the conductive layer forms at least one of a capacitor, a resistor and an inductor.
10. A semiconductor package, comprising:
a support substrate;
a stress relaxation layer provided on and in contact with a main surface of the support substrate;
a conductive layer provided on the stress relaxation layer;
a semiconductor device surrounded by the conductive layer and located on the stress relaxation layer;
an encapsulation material covering the semiconductor device, the encapsulation material being formed of an insulating material different from that of the stress relaxation layer;
a line layer arranged on the encapsulation material and electrically connected to the semiconductor device via an opening in the encapsulation material; and
an external terminal electrically connected to the line layer,
wherein the stress relaxation layer is provided with an opening formed in the vicinity of the semiconductor device.
11. The semiconductor package according to claim 10 , wherein the opening is an alignment mark, and has a polygonal shape having a side of a length of 480 μm or less or a circular shape having a diameter of 480 μm or less.