Six-transistor thyristor SRAM circuits and methods of operation
A memory cell based upon cross-coupled thyristors for an SRAM integrated circuit can be implemented in different combinations of MOS and bipolar select transistors with the thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM cells.
1. In an integrated circuit having at least one logic circuit operating within a MOSFET logic circuit range and a plurality of memory cells arranged in an array interconnected by a plurality of complementary bit line pairs and a plurality of word lines, each memory cell in the array connected a complementary bit line pair and a word line, each memory cell comprising:
a pair of cross-coupled thyristors, each thyristor having first and second semiconductor regions intermediate an anode and a cathode, a first intermediate region of one thyristor connected to the second intermediate region of the other thyristor and a second intermediate region of the one thyristor connected to the first intermediate region of the other thyristor, each thyristor having an anode connected to a first supply voltage and a cathode connected to a second supply voltage; and
a pair of select transistors, each select transistor connected between one of the complementary bit line pair, and a first intermediate region of one thyristor and a second intermediate region of the other thyristor, each select transistor having a control terminal connected to the word line;
wherein the memory cell has regions electrically biased so that voltage swings on the complementary bit line pair and the word line, operating within a magnitude of the MOSFET logic circuit range, are sufficient to read and write the memory cell.
2. The memory cell of claim 1 wherein the cathodes of the two thyristors are biased negatively approximately 0.5 volts with respect to the bottom of the MOSFET logic circuit range.
3. The memory cell of claim 1 wherein the anodes of the two thyristors are biased positively approximately 0.5 volts with respect to the top of the MOSFET logic circuit range.
4. The memory cell of claim 1 wherein the magnitude of the MOSFET logic circuit range is approximately 1 volt.
5. The memory cell of claim 4 wherein the MOSFET logic circuit range extends from approximately 0 to 1.0 volt.
6. The memory cell of claim 1 wherein the anode of one thyristor is connected to one of the complementary bit line pair, the anode of the other thyristor is connected to the other of the complementary bit line pair, and the cathodes of both thyristors are connected to the word line.
7. The memory cell of claim 1 wherein the anodes of both thyristors are connected to the word line, the cathode of one of the thyristors is connected to one of the complementary bit line pair, and the cathode of the other thyristor is connected to the other of the complementary bit line pair.
8. The memory cell of claim 1 wherein each of the select transistors comprises a bipolar transistor, the control terminal connected to a base region of the transistor.
9. The memory cell of claim 8 wherein each of the select transistor having a collector region connected to one of the complementary bit line pair and an emitter region connected to a first intermediate region of one thyristor.
10. The memory cell of claim 1 wherein each of the select transistors comprises a MOSFET transistor, the control terminal connected to the gate of the transistor.
11. The memory cell of claim 10 wherein each of the select transistors comprises a PMOS transistor.
12. For an integrated circuit having an array of SRAM memory cells interconnected by a plurality of complementary bit line pairs and a plurality of word lines, each SRAM cell having a pair of cross-coupled thyristors, each thyristor having first and second semiconductor regions intermediate an anode and a cathode, a first intermediate region of one thyristor connected to the second intermediate region of the other thyristor and a second intermediate region of the one thyristor connected to the first intermediate region of the other thyristor, each thyristor having an anode connected to a first supply voltage and a cathode connected to a second supply voltage, and a pair of select transistors, each select transistor connected between one of a complementary bit line pair, and the first intermediate region of one of the thyristors, and having a control terminal connected to a word line, a method of writing into an SRAM cell comprising:
selecting at least one SRAM cell;
providing for a difference between the first and second supply voltage greater than a standard core logic voltage range to the selected SRAM cell;
biasing the pair of select transistors of the selected SRAM cell so that the word line connected to the pair of select transistors to the selected SRAM cell is driven in a standard core logic voltage range; and
driving the bit line pairs connected to the selected SRAM cell in a standard core logic voltage range to turn the cross-coupled thyristors of the selected SRAM cell ON or OFF responsive to the logic state to be written into the selected SRAM cell;
whereby CMOS logic circuits can directly drive the plurality of complementary bit line pairs and the plurality of word lines.
13. The method of claim 12 wherein the standard core logic voltage range comprises 1 volt.
14. The method of claim 13 wherein the first and second supply voltage difference providing step comprises providing a difference of at least 1.4 volts.
15. The method of claim 12 wherein each of the select transistors comprises a bipolar transistor.
16. The method of claim 15 wherein the bipolar transistor having a collector region connected to one of the complementary bit line pair and an emitter region connected to a first intermediate region of one thyristor.
17. The method of claim 15 wherein the MOSFET transistor comprises a PMOS transistor.
18. The method of claim 12 wherein each of the select transistors comprises a MOSFET transistor.