Write assist thyristor-based SRAM circuits and methods of operation
A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with methods of operation. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM.
1. For an integrated circuit having an array of SRAM memory cells interconnected by a plurality of bit lines and a plurality of word lines, a method of writing into an SRAM cell comprising:
selecting at least one SRAM cell of the array, each SRAM cell having at least one thyristor, each thyristor having an anode and a cathode connected to a bit line and a word line in a cross point arrangement, a first intermediate region contiguous to the anode, and a second intermediate region between the first intermediate region and the cathode, the anode, cathode and intermediate regions having alternating polarities;
driving both the bit line and the word line connected to the selected SRAM cell to a voltage therebetween to turn the at least one thyristor of the selected SRAM cell ON and OFF responsive to the logic state to be written into the selected SRAM cell; and
providing during the driving step a conduction path between the anode and the second intermediate region, and around the first intermediate region, of the at least one thyristor that the charges are injected into, or removed from the second intermediate region, the conduction path providing the only conduction path around an intermediate region of the at least one thyristor;
whereby the at least one thyristor of the selected SRAM is assisted in being turned ON and OFF, and the writing into the selected SRAM cell is quickened.
2. The method of claim 1 wherein the anode of each SRAM cell in the array is connected to a bit line and the cathode of each SRAM cell in the array is connected to a word line.
3. The method of claim 1 wherein the anode of each SRAM cell in the array is connected to a word line and the cathode of each SRAM cell in the array is connected to a bit line.
4. The method of claim 1 wherein the conduction path providing step comprises turning on a MOSFET transistor connected between the anode and the second intermediate region of the at least one thyristor.
5. The method of claim 4 wherein the MOSFET transistor comprises a PMOS transistor.
6. The method of claim 1 wherein the plurality of bit lines comprises a plurality of complementary bit line pairs and wherein each SRAM cell further has a second thyristor having an anode connected to a complementary bit line or a word line and a cathode connected to a word line or the complementary bit line, the first intermediate region of the second thyristor connected to the second intermediate region of the at least one thyristor and the second intermediate region of the second thyristor connected to the first intermediate region of the at least one thyristor so that the two thyristors are cross-coupled, the method of writing into an SRAM cell further comprising:
simultaneously with the driving step for the at least one thyristor of the selected SRAM cell, driving the complementary bit line and the word line connected to the selected SRAM cell to a voltage therebetween complementary to that of the bit line and word line in the driving step for the at least one thyristor, to turn the second thyristor of the selected SRAM cell OFF and ON responsive to the logic state to be written into the selected SRAM cell; and
providing a conduction path between the anode and the second intermediate region, and around the first intermediate region, of the second thyristor so that the charges are removed from, or injected into, the second intermediate region of the second thyristor during the driving step, the conduction path providing the only conduction path around an intermediate region of the second thyristor;
whereby the second thyristor of the selected SRAM is assisted in being turned ON and OFF, and the writing into the selected SRAM cell is quickened.
7. The method of claim 6 wherein the anode of each SRAM cell in the array is connected to a bit line or its complementary bit line and the cathode of each SRAM cell in the array is connected to a word line.
8. The method of claim 6 wherein the anode of each SRAM cell in the array is connected to a word line and the cathode of each SRAM cell in the array is connected to a bit line or its complementary bit line.
9. The method of claim 6 wherein the conduction path providing step comprises turning on a second MOSFET transistor connected between the anode and the second intermediate region of the second thyristor.
10. The method of claim 9 wherein the second MOSFET transistor comprises a PMOS transistor.
11. For an integrated circuit having an array of SRAM memory cells interconnected by a plurality of bit lines and a plurality of word lines, a method of writing into an SRAM cell comprising:
selecting at least one SRAM cell of the array, each SRAM cell having at least one thyristor, each thyristor having a first terminal and a second terminal connected to a bit line and a word line in a cross point arrangement, a first intermediate region contiguous to the first terminal, and a second intermediate region between the first intermediate region and the second terminal, the first terminal, second terminal and intermediate regions having alternating polarities;
driving the bit line and the word line connected to the selected SRAM cell to a voltage therebetween to turn the at least one thyristor of the selected SRAM cell ON and OFF responsive to the logic state to be written into the selected SRAM cell; and
providing during the driving step a conduction path between the first terminal and the second intermediate region, and around the first intermediate region, of the at least one thyristor so that the charges are injected into, or removed from, the second intermediate region, the conduction path providing the only conduction path provided around an intermediate region of the least one thyristor;
whereby the at least one thyristor of the selected SRAM is assisted in being turned ON or OFF, and the writing into the selected SRAM cell is quickened.
12. The method of claim 11 wherein the first terminal of each SRAM cell in the array is connected to a bit line and the second terminal of each SRAM cell in the array is connected to a word line.
13. The method of claim 11 wherein the first terminal of each SRAM cell in the array is connected to a word line and the second terminal of each SRAM cell in the array is connected to a bit line.
14. The method of claim 11 wherein the conduction path providing step comprises turning on a MOSFET transistor connected between the first terminal and the second intermediate region of the at least one thyristor.
15. The method of claim 14 wherein the MOSFET transistor comprises a PMOS transistor.
16. The method of claim 11 wherein the plurality of bit lines comprises a plurality of complementary bit line pairs and wherein each SRAM cell further has a second thyristor having a first terminal connected to a complementary bit line or a word line and a second terminal connected to a word line or the complementary bit line, the first intermediate region of the second thyristor connected to the second intermediate region of the at least one thyristor and the second intermediate region of the second thyristor connected to the first intermediate region of the at least one thyristor so that the two thyristors are cross-coupled, the method of writing into an SRAM cell further comprising:
simultaneously with the driving step for the at least one thyristor of the selected SRAM cell, driving the complementary bit line and the word line connected to the selected SRAM cell to a voltage therebetween complementary to that of the bit line and word line in the driving step for the at least one thyristor, to turn the second thyristor of the selected SRAM cell OFF and ON responsive to the logic state to be written into the selected SRAM cell; and
providing a conduction path between the first terminal and the second intermediate region, and around the first intermediate region, of the second thyristor so that the charges are removed from, or injected into, the second intermediate region of the second thyristor during the driving step, the conduction path providing the only conduction path around an intermediate region of the second thyristor;
whereby the second thyristor of the selected SRAM is assisted in being turned ON and OFF, and the writing into the selected SRAM cell is quickened.
17. The method of claim 16 wherein the first terminal of each SRAM cell in the array is connected to a bit line or its complementary bit line and the second terminal of each SRAM cell in the array is connected to a word line.
18. The method of claim 16 wherein the first terminal of each SRAM cell in the array is connected to a word line and the second terminal of each SRAM cell in the array is connected to a bit line or its complementary bit line.
19. The method of claim 16 wherein the conduction path providing step comprises turning on a second MOSFET transistor connected between the first terminal and the second intermediate region of the second thyristor.
20. The method of claim 19 wherein the second MOSFET transistor comprises a PMOS transistor.