Semiconductor device and method of manufacturing semiconductor device
A semiconductor device including a semiconductor substrate, a first insulating layer formed over said semiconductor substrate, first grooves formed in said first insulating layer, a gate electrode and a first interconnect filled in said first grooves, respectively, a gate insulating film formed over said gate electrode, a semiconductor layer formed over said gate insulating, a second insulating layer formed over said semiconductor layer and said first insulating film, a via formed in said second insulating layer and connected to said semiconductor layer, a second groove formed in said second insulating layer, and a second interconnect filled in said second groove, formed over said via and connected to said via.
1. A semiconductor device comprising: a semiconductor substrate;
a first insulating layer formed over said semiconductor substrate;
first grooves formed in said first insulating layer; a gate electrode and a first interconnect filled in said first grooves, respectively;
a gate insulating film formed over said gate electrode; a semiconductor layer formed over said gate insulating;
a second insulating layer formed over said semiconductor layer and said first insulating film;
a via formed in said second insulating layer and connected to said semiconductor layer;
a second groove formed in said second insulating layer;
a second interconnect filled in said second groove, formed over said via and connected to said via; and
a trapping film formed over said semiconductor layer and a back-gate electrode formed over trapping film.
2. The semiconductor device as claimed in claim 1 ,
wherein said gate electrode and said first interconnect comprise Cu or Cu alloy and said gate insulating film functions as a Cu diffusion blocking film.
3. The semiconductor device as claimed in claim 1 ,
wherein said semiconductor layer includes a channel region, a source region and a drain region.
4. The semiconductor device as claimed in claim 1 ,
wherein said second interconnect is connected with said semiconductor layer thought said via.
5. The semiconductor device as claimed in claim 1 , wherein said trapping film comprises a SiN film.
6. The semiconductor device as claimed in claim 1 , wherein said back-gate electrode comprises a TiN film.
7. The semiconductor device as claimed in 1 , further comprising a mask pattern formed over said back-gate electrode.
8. The semiconductor device as claimed in claim 7 , wherein said mask pattern comprises a SiO film.
9. The semiconductor device as claimed in 1 , wherein said semiconductor layer, said gate insulating film, said gate electrode, said trapping film and said back-gate electrode configure a memory element.
10. The semiconductor device as claimed in claim 1 ,
wherein said gate electrode comprises Cu or Cu alloy.
11. The semiconductor device as claimed in claim 1 ,
wherein said semiconductor layer comprises at least one of an InGaZnO layer and a ZnO layer.
12. The semiconductor device as claimed in claim 1 ,
wherein said first insulating layer and second insulating layer comprise a low-k insulating layer having a dielectric constant less than a dielectric constant of silicon oxide, respectively.
13. The semiconductor device as claimed in claim 1 ,
wherein said gate electrode, said gate insulating film and said semiconductor layer function as a switching element.
14. The semiconductor device as claimed in claim 1 ,
further comprising a MOS (metal-oxide-semiconductor) transistor formed on said semiconductor substrate and formed under the first insulating film.
15. The semiconductor device as claimed in claim 14 ,
wherein at least a part of said MOS transistor overlaps with said semiconductor layer in a plan view.
16. A semiconductor device comprising: a semiconductor substrate;
a first insulating layer formed over said semiconductor substrate; grooves formed in said first insulating layer;
a gate electrode and a first interconnect filled in said grooves, respectively;
a gate insulating film formed over said gate electrode;
a semiconductor layer formed over said gate insulating;
a second insulating layer formed over said semiconductor layer and said first insulating film;
a via formed in said second insulating layer and connected to said semiconductor layer;
a second interconnect formed over said second insulating film and connected to said via; and
a trapping film formed over said semiconductor layer and a back-gate electrode formed over trapping film.
17. The semiconductor device as claimed in claim 16 ,
wherein said second interconnect is formed by AL or AL alloy.
18. The semiconductor device as claimed in claim 16 ,
wherein said gate electrode and said first interconnect comprise Cu or Cu alloy and said gate insulating film functions as a Cu diffusion blocking film.
19. The semiconductor device as claimed in claim 16 ,
wherein said semiconductor layer includes a channel region, a source region and a drain region.