IP Library Granted Patent US 9,362,200
Granted Patent B2
US 9,362,200 · App. 14/744,946 · Granted Jun 7, 2016

Heat sink in the aperture of substrate

Inventors: Hirokazu Honda (Kanagawa, JP); Shinji Watanabe (Kanagawa, JP); Toshihiro Iwasaki (Kanagawa, JP); Kiminori Ishido (Kanagawa, JP); Koichiro Niwa (Kanagawa, JP); Takeshi Miyakoshi (Kanagawa, JP); Sumikazu Hosoyamada (Kanagawa, JP); Yoshikazu Kumagaya (Kanagawa, JP); Tomoshige Chikai (Kanagawa, JP); Shingo Nakamura (Kanagawa, JP); Shotaro Sakumoto (Kanagawa, JP); Hiroaki Matsubara (Kanagawa, JP)
Assignee: J-DEVICES CORPORATION
H01L23/3675H01L23/3121H01L23/3677H01L23/49811H01L23/13H01L23/4006H01L23/49816H01L23/5389H01L2224/18
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Quick Facts
Patent No.
US 9,362,200
App. No.
14/744,946
Granted
Jun 7, 2016
Kind
B2
Abstract

A semiconductor package includes a support substrate arranged with a first aperture reaching a semiconductor device on a rear side, the semiconductor device is bonded via an adhesive to a surface of the support substrate, an insulating layer covering the semiconductor device, and wiring for connecting the semiconductor device and an external terminal through the insulating layer. The adhesive may form a part of the first aperture. In addition, a heat dissipation part may be arranged in the first aperture and a metal material may be filled in the first aperture.

Claims (33)

1. A semiconductor package comprising:

a support substrate arranged with a first aperture reaching a semiconductor device on a rear side;

the semiconductor device bonded via an adhesive to a surface of the support substrate;

an insulating layer covering the semiconductor device; and

a wiring on the insulating layer for connecting the semiconductor device and an external terminal via a contact hole in the insulating layer.

2. The semiconductor package according to claim 1 wherein the adhesive forms a part of the first aperture.

3. The semiconductor package according to claim 1 wherein part of the semiconductor device is exposed to the outside air through the first aperture.

4. The semiconductor package according to claim 1 wherein a heat dissipation part is arranged in the first aperture via a heat dissipation adhesive.

5. The semiconductor package according to claim 1 wherein a metallic material is filled into the first aperture.

6. The semiconductor package according to claim 1 wherein a conductive pattern covering the first aperture is arranged.

7. The semiconductor package according to claim 1 wherein the external terminal is a pin-shaped conductor or solder ball.

8. The semiconductor package according to claim 1 wherein the semiconductor device is a power device.

9. A semiconductor package comprising:

a support substrate arranged with a first aperture reaching a semiconductor device on a rear side;

the semiconductor device bonded via an adhesive to a surface of the support substrate;

an insulating layer covering the semiconductor device; and

a wiring for connecting the semiconductor device and an external terminal through the insulating layer,

wherein a second aperture reaching the semiconductor device is arranged on the insulation layer.

10. The semiconductor package according to claim 9 wherein a part of the semiconductor device is exposed to the outside air via the second aperture.

11. The semiconductor package according to claim 9 wherein a heat dissipation part is arranged in the second aperture.

12. A method of manufacturing a semiconductor package comprising:

bonding a semiconductor device on a surface of a support substrate via an adhesive;

covering the semiconductor device with an insulating layer;

forming a wiring on the insulating layer for connecting the semiconductor device and an external terminal via a contact hole in the insulating layer; and

forming a first aperture reaching the semiconductor device on a rear side of the support substrate.

13. The method of manufacturing a semiconductor package according to claim 12 wherein forming the first aperture reaching the semiconductor device on the rear surface side of the support substrate includes forming an aperture by etching the rear surface side of the support substrate and etching the adhesive using the aperture as a mask.

14. The method of manufacturing a semiconductor package according to claim 12 wherein a heat dissipation part is formed in the first aperture using heat dissipation adhesive after forming the first aperture.

15. The method of manufacturing a semiconductor package according to claim 12 wherein a metal material is filled into the first aperture after forming the first aperture.

16. The method of manufacturing a semiconductor package according to claim 12 wherein a conductive pattern covering the first aperture is formed after forming the first aperture.

17. The method of manufacturing a semiconductor package according to claim 12 wherein as second aperture is formed reaching the semiconductor device on the insulating layer.

18. The method of manufacturing a semiconductor package according to claim 17 wherein a heat dissipation part is formed in the second aperture.

19. The method of manufacturing a semiconductor package according to claim 12 wherein the external terminal is a pin-shaped conductor or solder ball.

20. The method of manufacturing a semiconductor package according to claim 12 wherein the semiconductor device is a power device.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE CONVEYING PARTY NAME PREVIOUSLY RECORDED AT REEL: 53597 FRAME: 184. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 5, 2021
From: J-DEVICES CORPORATION
To: AMKOR TECHNOLOGY JAPAN, INC.
Reel/Frame 055605/0060 →
CHANGE OF NAME Recorded Aug 25, 2020
From: J-DEVICES CO., LTD.
To: AMKOR TECHNOLOGY JAPAN, INC.
Reel/Frame 053597/0184 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 19, 2015
From: HONDA, HIROKAZU; WATANABE, SHINJI; IWASAKI, TOSHIHIRO; ISHIDO, KIMINORI; NIWA, KOICHIRO; MIYAKOSHI, TAKESHI; HOSOYAMADA, SUMIKAZU; KUMAGAYA, YOSHIKAZU; CHIKAI, TOMOSHIGE; NAKAMURA, SHINGO; SAKUMOTO, SHOTARO; MATSUBARA, HIROAKI
To: J-DEVICES CORPORATION
Reel/Frame 035930/0411 →
Priority Claims (1)
JP 2014-126480 · Jun 19, 2014 · national
Continuity (1)
Related Publication 20150371934A1 · Dec 24, 2015