Calibration techniques for SAR ADCs with on-chip reservoir capacitors
When reservoir capacitors are moved on-chip for individual bit decisions, a successive approximation register analog-to-digital converter (SAR ADC) has an addition source of error which can significantly affect the performance of the SAR ADC. Calibration techniques can be applied to measure and correct for such error in an SAR ADC using decide-and-set switching. Specifically, a calibration technique can expose the effective bit weight of each bit under test using a plurality of special input voltages and storing a calibration word for each bit under test to correct for the error. Such a calibration technique can lessen the need to store a calibration word for each possible output word to correct the additional source of error. Furthermore, another calibration technique can expose the effective bit weight of each bit under test without having to generate the plurality of special input voltages.
1. A method for measuring effective bit weights for calibrating a successive-approximation register analog-to-digital converter (SAR ADC) for digitizing an analog input of the SAR ADC, the method comprising:
measuring a first effective bit weight associated with first circuitry for generating a first bit of the SAR ADC, wherein during measuring of the first effective bit weight, first bit capacitors of the first circuitry sample the analog input of the SAR ADC and subsequently draw a first reference charge from a first on-chip reservoir capacitor of the first circuitry; and
after the first effective bit weight is measured, measuring a second effective bit weight associated with second circuitry for generating a second bit of the SAR ADC, wherein the second effective bit weight is isolated from the first effective bit weight and during the measuring of the second effective bit weight, second bit capacitors associated with the second bit of the second circuitry and other bit capacitors associated with bits less significant than the second bit sample the analog input of the SAR ADC against a common mode voltage and subsequently the second bit capacitors draw a second reference charge from a second on-chip reservoir capacitor of the second circuitry.
2. The method of claim 1 , further comprising:
based on the first effective bit weight and the second effective bit weight, generating and storing only one calibration word for correcting a bit weight error of the first bit of the SAR ADC and only one calibration word for correcting the bit weight error of the second bit of the SAR ADC.
3. The method of claim 1 , wherein:
top plates of the first and second bit capacitors are connectable to a comparator and the common mode voltage;
during the measuring of the first effective bit weight, bottom plates of the first bit capacitors are shorted together prior to drawing the first reference charge from the first on-chip reservoir capacitor; and
during the measuring of the second effective bit weight, bottom plates of the second bit capacitors are shorted together prior to drawing the second reference charge from the second on-chip reservoir capacitor.
4. The method of claim 1 , wherein:
measuring the first effective bit weight comprises sampling a first predetermined input at the analog input of the SAR ADC using the first circuitry; and
measuring the second effective bit weight comprises sampling a second predetermined input at the analog input of the SAR ADC using the second circuitry;
the second predetermined input is different from the first predetermined input; and
the second predetermined input forces a comparator for the first bit to be at zero differential.
5. The method of claim 4 , wherein the first predetermined input comprises a first differential input signal and the second predetermined input comprises a second differential input signal.
6. The method of claim 1 , wherein:
measuring the second effective bit weight comprises sampling a predetermined input at the analog input of the SAR ADC using the second circuitry, the second predetermined input corresponding to one or more bit weights of bits of the SAR ADC which are more significant than the second bit including a bit weight of the first bit, so that the one or more bit weights of the bit(s) which are more significant than the second bit do not contribute to the second effective bit weight being measured.
7. The method of claim 1 , wherein:
measuring the first effective bit weight comprises sampling a first predetermined input at the analog input of the SAR ADC using the first circuitry; and
measuring the second effective bit weight comprises removing the first effective bit weight from the measurement of the second effective bit weight and sampling the same first predetermined input at the analog input of the SAR ADC using the second circuitry.
8. The method of claim 7 , wherein:
the first predetermined input is differentially zero.
9. The method of claim 1 , wherein measuring the second effective bit weight comprises:
discharging the first reservoir capacitor of the first circuitry before measuring the second effective bit weight; and
connecting the first discharged reservoir capacitor to the bottom plates of the first bit capacitors before and/or when measuring the second effective bit weight.
10. The method of claim 1 , further comprising:
disconnecting the first on-chip reservoir capacitor from a positive reference and a negative reference and subsequently inserting the first on-chip reservoir capacitor differentially between the first bit capacitors during the measurement of the first effective bit weight; and
disconnecting the second on-chip reservoir capacitor from the positive reference and the negative reference and subsequently inserting the second on-chip reservoir capacitor differentially between the second bit capacitors during the measurement of the second effective bit weight.
11. The method of claim 1 , wherein measuring the second effective bit weight comprises:
configuring the first reservoir capacitor and connecting the first reservoir capacitor to the first bit capacitors such that the first reservoir capacitor delivers no charge to the first bit capacitors before and/or when measuring the second effective bit weight.
12. An apparatus for orthogonalizing bit weight errors of a successive-approximation register analog-to-digital converter (SAR ADC) for digitizing an analog input of the SAR ADC, the apparatus comprising:
means for exposing a first effective bit weight of a first bit of the SAR ADC by sampling a first predetermined input at the analog input to the SAR ADC by first bit capacitors, subsequently drawing a first reference charge from a first on-chip reservoir capacitor dedicated to the first bit capacitors to the first bit capacitors; and
means for exposing a second effective bit weight of a second bit of the SAR ADC after exposing the first effective weight of the first bit by removing contribution of the first bit to measurement of the second effective bit weight, sampling a second predetermined input at the analog input to the SAR ADC by second bit capacitors, subsequently drawing a second reference charge from a second on-chip reservoir capacitor dedicated to the second bit capacitors to the second bit capacitors, and setting bits less significant to the second bit to complement the second bit.
13. The apparatus of claim 12 , wherein:
sampling the first predetermined input at the analog input of the SAR ADC by the first bit capacitors comprises sampling the first predetermined input against a common mode voltage; and
exposing the first effective bit weight further comprises, after disconnecting the first bit capacitors from the common mode voltage and the analog input of the SAR ADC and prior to drawing the first reference charge from the first on-chip reservoir capacitor, shorting the first bit capacitors together to allow a comparator connected to the first bit capacitors to output a decision for inserting the second on-chip reservoir capacitor in one of two ways.
14. The apparatus of claim 12 , further comprising:
means for recording bit trial results of the bits less significant to the first bit when the first bit effective weight of the first bit is being exposed;
means for recording bit trial results of the bit less significant to the second bit when the second bit effective weight of the second bit is being exposed; and
means for generating only two calibration words based on the bit trial results to calibrate the first bit and the second bit.
15. The apparatus of claim 12 , further comprising:
signal generating means for generating the first predetermined input and the second predetermined input.
16. The apparatus of claim 12 , wherein removing contribution of the first bit comprises:
generating the second predetermined input to correspond to one or more bit weights of bits of the SAR ADC which are more significant than the second bit including a bit weight of the first bit.
17. The apparatus of claim 12 , wherein:
the second predetermined input is the same as the first predetermined input.
18. The apparatus claim 17 , further comprising:
means provided on-chip with the SAR ADC for generating the first predetermined input and the second predetermined input, wherein the first predetermined input is differentially zero and the second predetermined input is differentially zero.
19. The apparatus of claim 12 , wherein removing the contribution of the first bit comprises:
configuring the first reservoir capacitor and connecting the first reservoir capacitor to the first bit capacitors such that the first reservoir capacitor delivers no charge to the first bit capacitors before and/or when measuring the second bit weight error associated with the second bit capacitors and the second on-chip reservoir capacitor.
20. A successive-approximation register analog-to-digital converter (SAR ADC), the SAR ADC comprising:
circuitry to converting an analog input to the SAR ADC to a digital output comprising bit capacitors and reservoir capacitors, each reservoir capacitor provided for a different bit of the SAR ADC, wherein for at least one of the bit capacitors, the bit capacitor samples the analog input to the SAR ADC and draws reference charge from a reservoir capacitor provided for the bit capacitor; and
a calibration sequencer to expose an effective bit weight of a second bit by implementing a switching sequence that:
configures a first reservoir capacitor provided for a first bit to deliver no charge to a first bit capacitors associated with the first bit, and
records decisions of bits lesser than the second bit balancing only the effective bit weight of the second bit, wherein the decisions are a measurement of the effective bit weight of the second bit.
21. The SAR ADC of claim 20 , wherein the reservoir capacitors comprises:
the first reservoir capacitor dedicated to first bit capacitors associated with the first bit; and
a second reservoir capacitor dedicated to second bit capacitors associated with the second bit.
22. The SAR ADC of claim 20 , the circuitry further comprises:
a comparator connectable to the first bit capacitors, the second bit capacitors, and other bit capacitors for performing the decisions.
23. The SAR ADC of claim 20 , wherein the switching sequence further implements the following steps:
charging a second reservoir capacitor provided for the second bit with a positive reference and a negative reference;
sampling the analog input by second bit capacitors and bit capacitors associated with bits lesser than the second bit against a common mode voltage;
shorting of the second bit capacitors after sampling step; and
connecting the first bit capacitors to the first reservoir capacitor and connecting second bit capacitors associated with the second bit to the second reservoir capacitor after the shorting step.
24. The method of claim 1 , wherein:
the first bit capacitors are connectable to the analog input of the SAR ADC and a comparator; and
the second bit capacitors are connectable to the analog input of the SAR ADC and the comparator.
25. The method of claim 1 , wherein:
the first on-chip reservoir capacitor has top and bottom plates which are connectable to a positive reference and a negative reference respectively to store the first reference charge; and
the second on-chip reservoir capacitor has top and bottom plates which are connectable to the positive reference and the negative reference respectively to store the second reference charge.
26. The method of claim 1 , wherein during the measuring of the first effective bit weight, the first bit capacitors and other bit capacitors associated with bits less significant than the first bit sample the analog input of the SAR ADC against a common mode voltage prior to the first bit capacitors drawing the first reference charge.