Memory circuit for reading ferroeletric memory having gain element including feedback capacitor
A memory circuit has a ferroelectric memory cell having a word line and a bit line, an input transistor connected to the bit line, a gain element electrically connected the bit line, wherein the gain element includes a feedback capacitor, and an output terminal. A method of reading a memory cell includes applying a voltage to a word line of the memory cell, causing charge to transfer from the memory cell to a feedback capacitor, generating a voltage, amplifying the voltage by applying a gain having a magnitude of less than three, sensing an output voltage at an output node to determine a state of the memory cell, and storing the memory state in a latch.
1. A memory circuit, comprising:
an output terminal; and
a memory circuit core electrically connected to the output terminal, comprising:
a ferroelectric memory cell between a word line and a bit line;
a voltage generator connected between the word line and a ground; and
a gain element electrically connected to the bit line, wherein the gain element has a feedback capacitor connected between the bit line and the output terminal, and a single transistor connected between the bit line and the output terminal, wherein an output of the memory cell is read at the output terminal.
2. The memory circuit of claim 1 , further comprising a latch electrically connected to the output terminal.
3. The memory circuit of claim 2 , wherein the latch comprises a pair of cross-coupled transistors.
4. The memory circuit of claim 1 , further comprising a reset transistor connected to the bit line of the memory cell.
5. The memory circuit of claim 1 , wherein the feedback capacitor value is selected to cause a bias across the memory cell during a read operation sufficient to write the memory cell.
6. The memory circuit of claim 1 , wherein the memory circuit is implemented in a single transistor polarity.
7. The memory circuit of claim 1 , further comprising at least one power switch connected to the memory circuit to turn off the memory circuit.
8. The memory circuit of claim 1 , wherein the at least one power switch comprises three power switches.
9. The memory circuit of claim 1 , wherein the input transistor comprises a thin film transistor.
10. The memory circuit of claim 9 , wherein the thin film transistor comprises a solution-processed thin film transistor.
11. The memory circuit of claim 1 , wherein the memory circuit comprises an integrated, thin film transistor memory circuit.
12. A method of reading a memory cell, comprising:
applying a voltage to a word line of the memory cell, causing charge to transfer from the memory cell to a feedback capacitor in a gain element, generating a voltage;
amplifying the voltage by applying a gain having a magnitude of less than three using the gain element having the feedback capacitor and a single transistor;
sensing an output voltage at an output terminal to read a state of the memory cell; and
storing the memory state in a latch.
13. The method of claim 12 , wherein applying the voltage to the word line causes the memory cell to be written to a memory state.
14. A memory circuit, comprising:
an output terminal; and
a memory circuit core, comprising:
a ferroelectric memory cell between a word line and a bit line;
an input transistor connected to the bit line; and
a gain element electrically connected the bit line, wherein the gain element has a feedback capacitor connected between the bit line and the output terminal, and a has a gain of three or less, wherein an output of the memory cell is read at the output terminal.
15. The memory circuit of claim 14 , further comprising a latch electrically connected to the output terminal.
16. The memory circuit of claim 15 , wherein the latch comprises a pair of cross-coupled transistors.
17. The memory circuit of claim 14 , further comprising a reset transistor connected to the bit line of the memory cell.
18. The memory circuit of claim 14 , wherein the memory circuit is implemented in a single transistor polarity.