Structures and methods for reliable packages

1. A method of forming a plurality of packages, the method comprising:

etching one or more cavities in a first side of a substrate device, the substrate device including conductive vias formed in a substrate;

mounting chip devices to the first side of the substrate device to electrically contact the conductive vias;

depositing an encapsulation layer over the chip devices and filling the cavities;

planarizing a second side to reveal the conductive vias on the second side; and

singulating through the cavities to form said packages separated from each other, with each package having one or more of said chip devices mounted on a respective singulated substrate device.

2. The method of claim 1 , wherein a redistribution layer is formed over the conductive vias on the substrate device.

3. The method of claim 2 , wherein mounting chip devices includes mounting chip devices to the redistribution layer.

4. The method of claim 1 , wherein the cavities are etched to a depth into the substrate that is equal to or exceeds that of the conductive vias to form an isolation bridge.

5. The method of claim 1 , wherein the cavities are etched to a depth into the substrate that is less than that of the conductive vias to form a substrate bridge.

6. The method of claim 1 , further including forming a redistribution layer, back end-of-line layer, or bonding layer over the conductive vias on the second side prior to singulating.

7. A method of forming a plurality of packages, the method comprising:

mounting a wafer to a first side of a first substrate device to electrically contact with first conducting vias formed in the substrate device;

planarizing a second side of the first substrate device to reveal the first conducting vias on the second side;

etching one or more cavities in the second side of the first substrate device;

depositing an encapsulation layer on the second side of the first substrate device; and

singulating through the cavities to form said packages separated from each other, with each package having one or more chip devices mounted on a respective singulated substrate device.

8. The method of claim 7 , further including forming a first redistribution layer in electrical contact with the first conducting vias on the second side of the first substrate device and wherein etching one or more cavities in the second side of the first substrate device includes etching through the first redistribution layer.

9. The method of claim 8 , further including mounting devices onto the first redistribution layer.

10. The method of claim 8 , further including mounting a second substrate device, the second substrate device including second conducting vias formed in the second substrate device and cavities formed in the second substrate device, wherein the cavities in the second substrate device align with cavities in the first substrate device.

11. The method of claim 10 , wherein the second substrate device includes a second redistribution layer that electrically contacts the first redistribution layer.

12. The method of claim 1 wherein said mounting is performed after said etching.

13. The method of claim 12 wherein said planarizing is performed after said etching.

14. The method of claim 1 wherein said depositing is performed after said mounting.

15. The method of claim 1 wherein said planarizing is performed after said mounting.

16. The method of claim 1 wherein said planarizing is performed after said depositing.

17. The method of claim 7 wherein said depositing comprises depositing said encapsulation layer into the cavities.

18. The method of claim 7 wherein the cavities enter the wafer.

19. The method of claim 10 wherein said singulating is performed through the aligned cavities in the first and second substrate devices.

20. The method of claim 19 wherein before said singulating, the cavities in the second substrate device contain encapsulation material.