HIGH VOLTAGE FINFET STRUCTURE WITH SHAPED DRIFT REGION
Devices and methods for a high voltage FinFET with a shaped drift region include a lateral diffusion metal oxide semiconductor (LDMOS) FinFET having a substrate with a top surface and a fin attached to the top surface. This fin includes a source region having a first type of doping, an undoped gate-control region adjacent the source region, a drift region adjacent the undoped gate-control region opposite the source region, and a drain region. The amount of doping of the source region is greater than the amount in the drift region. The drain region has the same type of doping and is adjacent the drift region. The fin in the drift region is tapered, being wider closest to the undoped gate-control region and thinner closest to the drain region. A gate stack is attached to the top surface of the substrate and located with the undoped gate-control region.
1 - 12 . (canceled)
13 . A method comprising:
providing a substrate of semiconductor material, said substrate having a top surface;
forming a fin on said substrate, said fin having a height above said top surface of said substrate;
doping a first portion of said fin with a first type of doping, said first portion of said fin comprising a source region;
forming a gate conductor on said substrate, said gate conductor being formed around an undoped gate-control portion of said fin adjacent to said source region;
forming a drift region in said fin adjacent to said undoped gate-control portion of said fin, said undoped gate-control portion of said fin being between said source region and said drift region, said drift region having said first type of doping, said source region being more heavily doped relative to said drift region;
doping a second portion of said fin adjacent to said drift region with said first type of doping, said second portion of said fin comprising a drain region, said drift region being between said undoped gate-control portion of said fin and said drain region; and
tapering said drift region, said drift region having a first width close to said undoped gate-control portion of said fin and a second width close to said drain region, said second width being less than said first width.
14 . The method according to claim 13 , said forming said fin on said substrate further comprising:
depositing an undoped conductive layer on said substrate;
planarizing said undoped conductive layer; and
etching said undoped conductive layer to expose said fin.
15 . The method according to claim 13 , said tapering said drift region further comprising:
depositing an oxide layer on said fin between said undoped gate-control portion of said fin and said drain region; and
depositing a nitride layer on said oxide layer.
16 . The method according to claim 13 , said drift region being tapered in height, said fin being taller, relative to said top surface, closest to said undoped gate-control portion of said fin and shorter, relative to said top surface, closest to said drain region.
17 . The method according to claim 13 , further comprising:
forming a trench isolation structure in said top surface of said substrate, said fin being bounded by said trench isolation structure.
18 . The method according to claim 13 , further comprising:
doping n-type versions of said fin; and
doping p-type versions of said fin.
19 . The method according to claim 13 , further comprising:
applying a mask to a portion of said fin, said mask protecting said undoped gate-control portion of said fin and said drift region; and
epitaxially growing silicon sections in said source region and said drain region.
20 . The method according to claim 13 , further comprising:
applying contacts to said source region, said drain region, and said gate conductor.