High speed gallium nitride transistor devices
View Patent ↗A low leakage current switch device ( 110 ) is provided which includes a GaN-on-Si substrate ( 11 - 43 ) covered by a passivation surface layer ( 43 ) in which a T-gate electrode with sidewall extensions ( 48 ) is formed and coated with a conformal passivation layer ( 49 ) so that the T-gate electrode sidewall extensions are spaced apart from the underlying passivation surface layer ( 43 ) by the conformal passivation layer ( 49 ).
1. A semiconductor device, comprising:
a substrate comprising one or more active areas with a gallium nitride layer;
a passivation surface layer covering the gallium nitride layer with a gate electrode opening defined by passivation surface layer sidewalls separated by a first width;
a conductive gate electrode located at least in part in the gate electrode opening to be in contact with the gallium nitride layer, where the conductive gate electrode comprises a lower contact base having vertical sidewalls and upper gate electrode sidewall extensions formed to be vertically spaced apart from the passivation surface layer by a minimum vertical gap distance;
a first patterned metal layer defining one or more bottom capacitor plate layers which are electrically isolated from the substrate;
one or more passivation layers located on at least a portion of the vertical sidewalls of the contact base and on a top surface of the one or more bottom capacitor plate layers; and
a second patterned metal layer defining one or more top capacitor plate layers which are separated from the one or more bottom capacitor plate layers by the one or more passivation layers.
2. The semiconductor device of claim 1 , where the contact base has a width that is narrower than the first width such that the one or more passivation layers cover the entirety of the vertical sidewalls of the contact base.
3. The semiconductor device of claim 1 , where contact base has a width that is equal to the first width such that the one or more passivation layers cover vertical sidewalls of the contact base except where the contact base is in direct contact with the passivation surface layer sidewalls.
4. The semiconductor device of claim 1 , where the one or more passivation layers located on the vertical sidewalls of the contact base have a total thickness that is controlled to prevent an increase in total gate capacitance by more than 10% as compared to a conductive gate electrode that does not have one or more passivation layers located on the vertical sidewalls of the contact base.
5. A gallium nitride transistor device, comprising:
a substrate comprising an epitaxial gallium nitride surface layer;
a passivation surface layer covering the epitaxial gallium nitride surface layer except for a gate contact opening and source/drain contact openings;
a conductive gate electrode comprising:
a contact base portion formed over the epitaxial gallium nitride surface layer in the gate contact opening, and
gate electrode sidewall extensions that overlap with the passivation surface layer and are vertically spaced above the passivation surface layer by a vertical gap;
a first plurality of patterned conductor layers defining (1) source/drain electrode layers in electrical contact with the epitaxial gallium nitride surface layer through the source/drain contact openings and (2) one or more bottom capacitor plate layers which are electrically isolated from the substrate;
a passivation layer covering exposed sidewall surfaces of the conductive gate electrode and a top surface of the one or more bottom capacitor plate layers, wherein a portion of the passivation layer is formed on a vertical sidewall of the contact base portion located below the gate electrode sidewall extensions; and
a second plurality of patterned conductor layers defining (1) additional source/drain electrode layers in ohmic contact with the source/drain electrode layers and (2) one or more top capacitor plate layers which are separated from the one or more bottom capacitor plate layers by the passivation layer.
6. The gallium nitride transistor device of claim 5 , where the substrate comprises an upper gallium nitride cap layer, a middle aluminum gallium nitride barrier layer, and an underlying gallium nitride buffer layer.
7. The gallium nitride transistor device of claim 5 , where the passivation surface layer comprises a layer of low-pressure chemical vapor deposition silicon nitride having a thickness of about 50-150 Å.
8. The gallium nitride transistor device of claim 5 , where the conductive gate electrode comprises a Schottky gate electrode comprising nickel.
9. The gallium nitride transistor device of claim 5 , where the passivation layer comprises a low hydrogen content and low ionic or electronic charge content passivation layer having a thickness of approximately 300 Å.
10. The gallium nitride transistor device of claim 5 , where the gate electrode sidewall extensions are vertically spaced apart from the passivation surface layer by a vertical gap and where the contact base portion of the conductive gate electrode is laterally separated from the passivation surface layer by a lateral gap.
11. The gallium nitride transistor device of claim 5 , where the contact base portion of the conductive gate electrode comprises a bottom diffusion barrier metal layer and an upper Schottky metal layer.
12. The gallium nitride transistor device of claim 10 , where the passivation layer is located in the lateral gap.
13. The gallium nitride transistor device of claim 5 , where the one or more bottom capacitor plate layers are located over an isolation region formed in the substrate.
14. The gallium nitride transistor device of claim 5 , further comprising one or more conformal dielectric layers formed on the passivation layer covering exposed sidewall surfaces of the conductive gate electrode to form a vertical metal-insulator-semiconductor (MIS) sandwich along the vertical edges of the contact base portion of the conductive gate electrode to reduce leakage and ensure high-voltage operation.
15. The gallium nitride transistor device of claim 5 , where each of the one or more top capacitor plate layers which are separated from the one or more bottom capacitor plate layers by the passivation layer comprise a Metal-Insulator-Metal capacitor.
16. A integrated circuit device, comprising:
a semiconductor layer comprising an elevated mesa section comprising a gallium nitride surface layer;
a passivation surface layer covering the covering the elevated mesa section, where the passivation surface layer comprises a gate contact opening and source/drain contact openings defined to expose the gallium nitride surface layer;
a conductive gate electrode positioned within the gate contact opening, where the conductive gate electrode comprises a gate length contact base having a gate length and gate electrode sidewall extensions formed to be vertically spaced apart from the passivation surface layer by a minimum vertical gap distance Y GATE ;
a first plurality of patterned conductor layers defining (1) source/drain electrode layers in electrical contact with the gallium nitride surface layer and (2) one or more bottom capacitor plate layers which are electrically isolated from the semiconductor layer;
one or more passivation layers covering exposed sidewall surfaces of the conductive gate electrode and the one or more bottom capacitor plate layers; and
a second plurality of patterned conductor layers defining (1) additional source/drain electrode layers in ohmic contact with the source/drain electrode layers and (2) one or more top capacitor plate layers which are separated from the one or more bottom capacitor plate layers by the one or more passivation layers.
17. The integrated circuit device of 16 , where the gate length contact base is in direct contact with the passivation surface layer in the gate contact opening.
18. The integrated circuit device of 17 , where the one or more passivation layers on the conductive gate electrode cover exposed sidewall surfaces of the conductive gate electrode except where the gate length contact base is in direct contact with the passivation surface layer.
19. The integrated circuit device of 16 , where the gate length contact base is laterally spaced apart from the passivation surface layer in the gate contact opening.
20. The integrated circuit device of 19 , where the one or more passivation layers on the conductive gate electrode cover exposed sidewall surfaces of the conductive gate electrode including the exposed gate length contact base that is laterally spaced apart from the passivation surface layer.