Systems, methods, and apparatuses for last branch record support compatible with binary translation and speculative execution using an architectural bit array and a write bit array

1. A hardware processor core comprising:

a hardware execution unit to execute a branch instruction;

at least two last branch record (LBR) registers to store source and destination information of a branch taken during program execution, wherein an entry in a LBR register is to include an encoding of the branch;

an architectural bit array to indicate which LBR register is architecturally correct;

a write bit array to indicate when an LBR register has been written; and

a plurality of top of stack pointers to indicate which LBR register in a LBR register stack is to be written.

2. The hardware processor core of claim 1 , wherein the encoding of the branch is to indicate when the branch is a native instruction to instruction set architecture of the processor core.

3. The hardware processor core of claim 1 , further comprising:

a binary translator to translate the branch instruction from a first instruction set architecture instruction to a second instruction set architecture instruction.

4. The hardware processor core of claim 3 , wherein the first and second instruction set architectures are a same instruction set architecture.

5. The hardware processor core of claim 1 , wherein the encoding of the branch is to indicate when the branch is a non-native instruction to instruction set architecture of the processor core.

6. The hardware processor core of claim 5 , wherein the encoding is one of a conditional jump, near relative call, near indirect call, near return, near indirect jump, near relative jump, and far branch.

7. The hardware processor core of claim 1 , wherein the entry in the LBR register is to include a polarity bit.

8. The hardware processor core of claim 1 , wherein the hardware processor core is to support speculative execution.

9. The hardware processor core of claim 1 , wherein the entry in the LBR register is to include a value that corresponds to which translated instruction was executed, an offset which is a physical address into a translated code cache, and an emulated native instruction pointer at the time of the branch.

10. A method comprising:

executing native instructions;

beginning a speculative block of code;

executing a branch in the speculative block of code;

writing information about the executed branch in a last branch record (LBR) according to a top of stack pointer and architectural bit settings that align with the top of stack pointer;

setting a corresponding write bit in a write bit array;

determining the speculative block of code is to commit;

exclusive ORing the write bit array with an architectural array and storing a result of the exclusive ORing in the architectural array;

clearing the write bit array; and

copying the top of stack pointer from a first top of stack register to a second top of stack register.

11. The method of claim 10 , wherein the speculative block of code is denoted by an XBEGIN instruction.

12. The method of claim 10 , wherein information about the executed branch includes an encoding of the branch and source and destination information of the branch.

13. The method of claim 10 , wherein determining the speculative block of code is to commit is performed in response to an XEND instruction.

14. The method of claim 10 , wherein the native instructions are X86 instructions.