Pipelined decoder and method for conditional storage
View Patent ↗A pipelined decoder for storaging of soft bits and hard bits associated with code blocks of a transmission. The proposed circuit reduces the amount of memory needed at the receiver level for soft bits and hard bits, in a pipelined decoder. Namely, with the solution of the subject application, both the LLRs and hard bits associated with a given code block are available when the CRC value is determined. Hence, the effect obtained non-pipelined decoder is achieved by the pipelined decoder of the subject application. A receiver for a wireless communication system, a method and a computer program are also disclosed.
1. A receiver for a wireless communication system, the receiver comprising:
first, second and third memory locations, each being arranged to store information associated with one received block of a transmission signal;
a Log-Likelihood Ratio, LLR, computing unit arranged to provide soft bits based on a received block of the transmission signal;
a Hybrid Automatic Repeat Request, HARQ, combining unit operably coupled to the LLR computation unit and to the first, second and third memory locations, the HARQ combining unit being arranged to:
combine the soft bits with a retransmission of the received block; and,
store the combined soft bits into a cyclically selected one of the first, second and third memory locations;
a Forward Error Correction, FEC, decoding unit operably coupled to the first, second and third memory locations, the FEC decoding unit being arranged to:
decode combined soft bits into hard bits based on a previous cyclically selected memory location of the first, second and third memory locations; and,
provide a cyclic redundancy check, CRC, value of the hard bits;
a processing unit, such as a processor, operably coupled to the FEC decoding unit and the first, second and third memory locations, the processing unit being arranged to store in an external memory:
the combined soft bits of the previously cyclically selected memory location when the CRC value is representative of a CRC failure; and,
the hard bits when the CRC value is representative of a CRC success, wherein storage of the combined soft bits and the hard bits is deferred until after the CRC failure or CRC success, respectively, reducing the amount of memory required for the soft bits and the hard bits,
wherein, in operation,
the HARQ combining unit and FEC decoding unit concurrently operate on soft bits associated with different blocks of the transmission signal.
2. The receiver of claim 1 , wherein cyclically accessing the first, second and third memory locations, for storing and decoding, is performed according to a given scheme.
3. The receiver of claim 1 , wherein the communication channel is a Long Term Evolution, LTE, communication system.
4. The receiver of claim 3 , wherein the block is any one of a: Physical Uplink Shared channel, PUSCH, or Physical Downlink Shared Channel, PDSCH, code block.
5. A pipelined decoder for storing soft bits and hard bits associated with blocks of a transmission, the pipelined decoder comprising:
an input for providing first, second and third memory locations, each being arranged to store information associated with one received block of the transmission;
a logic circuit for computing soft bits based on a received block of the transmission;
a logic circuit for combining the soft bits with a retransmission of the received block;
a logic circuit for storing the combined soft bits into a cyclically selected one of the first, second and third memory locations;
a decoder for decoding combined soft bits into hard bits based on the previous cyclically selected memory location;
a Forward Error Correction, FEC, decoding unit for providing a cyclic redundancy check, CRC, value of the hard bits;
an output for storing in an external memory:
the combined soft bits of the previous cyclically selected memory location when the CRC value is representative of a CRC failure; and,
the hard bits when the CRC value is representative of a CRC success, wherein storage of the combined soft bits and the hard bits is deferred until after the CRC failure or CRC success, respectively, reducing the amount of memory required for the soft bits and the hard bits,
wherein, in operation,
the logic circuit for combining and the decoder are concurrently operated on soft bits associated with different blocks of the transmission.
6. The pipelined decoder of claim 5 , wherein cyclically accessing the first, second and third memory locations, for storing and decoding, is performed according to a given scheme.
7. The pipelined decoder of claim 5 , wherein the communication channel is a Long Term Evolution, LTE, communication system.
8. The pipelined decoder of claim 7 , wherein the block is any one of a: Physical Uplink Shared channel, PUSCH, or Physical Downlink Shared Channel, PDSCH, code block.
9. A method of storing soft bits and hard bits associated with blocks of a transmission, the method comprising:
providing first, second and third memory locations, each being arranged to store information associated with one received block of the transmission;
computing soft bits based on a received block of the transmission;
combining the soft bits with a retransmission of the received block;
storing the combined soft bits into a cyclically selected one of the first, second and third memory locations;
decoding combined soft bits into hard bits based on a previous cyclically selected memory location of the first, second and third memory locations;
providing a cyclic redundancy check, CRC, value of the hard bits;
storing in an external memory:
the combined soft bits of the previous cyclically selected memory location when the CRC value is representative of a CRC failure; and,
the hard bits when the CRC value is representative of a CRC success, wherein storage of the combined soft bits and the hard bits is deferred until after the CRC failure or CRC success, respectively, reducing the amount of memory required for the soft bits and the hard bits,
wherein,
combining and decoding operations are concurrently performed on soft bits associated with different blocks of the transmission.
10. The method of claim 9 wherein, cyclically accessing the first, second and third memory locations, for storing and decoding, is performed according to a given scheme.
11. The method of claim 9 , wherein the communication channel is a Long Term Evolution, LTE, communication system.
12. The method of claim 11 , wherein the block is any one of a: Physical Uplink Shared channel, PUSCH, or Physical Downlink Shared Channel, PDSCH, code block.
13. A computer program product stored in a non-transitory computer-readable storage medium that stores computer-executable code for storing soft bits associated with blocks of a transmission, the computer-executable process causing a processor computer to perform the method according to claim 9 .
14. The receiver of claim 2 , wherein the communication channel is a Long Term Evolution, LTE, communication system.
15. The pipelined decoder of claim 6 , wherein the communication channel is a Long Term Evolution, LTE, communication system.
16. The method of claim 10 , wherein the communication channel is a Long Term Evolution, LTE, communication system.