Methods for forming arrays of small, closely spaced features
View Patent ↗Methods of forming arrays of small, densely spaced holes or pillars for use in integrated circuits are disclosed. Various pattern transfer and etching steps can be used, in combination with pitch-reduction techniques, to create densely-packed features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed patterns of crossing elongate features with pillars at the intersections. Spacers are simultaneously applied to sidewalls of both sets of crossing lines to produce a pitch-doubled grid pattern. The pillars facilitate rows of spacers bridging columns of spacers.
1. A method of semiconductor processing, comprising:
forming a mandrel on an underlying substrate, comprising:
on a first level of the substrate, forming a grid of intersecting lines of material over an upper surface of the substrate, the grid of intersecting lines comprising first lines extending along a first direction and second lines extending along a second direction that crosses the first direction, the first and second lines extending to a first elevation above the upper surface of the substrate; and
on a second level of the substrate, forming pillars on the substrate that extend upwards- from intersections of the intersecting lines to a second elevation above the upper surface of the substrate; and
forming spacers on the substrate at sidewalls of the mandrel, the spacers being formed on sidewalls of the intersecting lines and on sidewalls of the pillars, wherein forming spacers comprises:
blanket depositing a layer of spacer material over the mandrel;
and directionally etching the layer of spacer material to define the spacers at the sidewalls of the mandrel.
2. The method of claim 1 , wherein the spacers form loops around the pillars and around interior walls of the grid of intersecting lines.
3. The method of claim 2 , wherein the spacers extend continuously from the first level to the second level.
4. The method of claim 1 , wherein the intersecting lines comprise a first plurality of lines orthogonal to a second plurality of lines.
5. The method of claim 1 , wherein forming the spacers exposes upper surfaces of the mandrel, and further comprising selectively removing exposed portions of the mandrel.
6. The method of claim 1 , wherein the grid of intersecting lines and the pillars are formed of a same material.
7. The method of claim 6 , wherein the grid of intersecting lines and the pillars comprise amorphous carbon.
8. The method of claim 1 , wherein the spacers comprise an oxide.
9. The method of claim 1 , wherein forming the mandrel comprises etching a single layer of material, wherein the grid of intersecting lines and the pillars are formed in that layer of material.
10. A method of semiconductor processing, comprising:
forming first lines extending along a first direction over an upper surface of a substrate and second lines extending along a second direction, the second lines crossing the first lines to form a grid of intersecting lines of a single sacrificial material;
forming pillars on the substrate that extend upwards from the intersections of the intersecting lines of sacrificial material; and
forming spacers on the substrate at sidewalls of the grid and pillars, wherein forming spacers comprises:
blanket depositing a layer of spacer material over the mandrel;
and directionally etching the layer of spacer material to define the spacers at the sidewalls of the mandrel.
11. The method of claim 10 , further comprising:
preferentially etching exposed portions of the pillars and the grid of intersecting lines to leave a pattern defined by the spacers; and
transferring the pattern to an underlying material.
12. The method of claim 11 , wherein transferring the pattern forms holes in the underlying material.
13. The method of claim 12 , further comprising depositing conductive material into the holes.
14. The method of claim 12 , further comprising depositing phase change material into the holes.
15. The method of claim 11 , wherein transferring the pattern defines an array of features in a memory array.
16. The method of claim 14 , wherein the memory array is a flash memory array.
17. The method of claim 10 , wherein the spacers have a width of about 20-60 nm.
18. The method of claim 10 , wherein the sacrificial material is a carbon-containing material.
19. The method of claim 18 , wherein the carbon-containing material is amorphous carbon.