IP Library Granted Patent US 9,455,241
Granted Patent B2
US 9,455,241 · App. 14/754,230 · Granted Sep 27, 2016

Integrated circuit package and method of forming the same

Inventors: Yonggang Jin (Singapore, SG); Kiyoshi Kuwabara (Kanagawa, JP); Xavier Baraton (Moirans, FR)
Assignee: STMICROELECTRONICS PTE LTD
H01L24/83H01L21/311H01L21/486H01L21/4821H01L21/56H01L21/568H01L21/6835H01L21/768H01L23/49816H01L23/49827H01L23/49894H01L23/5389H01L24/11H01L24/18H01L24/82H01L24/96H01L2221/68345H01L2221/68359H01L2221/68372H01L2221/68377H01L2221/68381H01L2224/18H01L2224/8385H01L2924/01006H01L2924/01013H01L2924/01029H01L2924/01033H01L2924/01047H01L2924/01078H01L2924/01079H01L2924/01082H01L2924/09701H01L2924/14H01L2924/15311H01L2924/181H01L2924/19041H01L2924/19042H01L2924/19043
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Quick Facts
Patent No.
US 9,455,241
App. No.
14/754,230
Granted
Sep 27, 2016
Kind
B2
Abstract

Aspects of the invention are directed towards an integrated circuit package and method of forming the same, and more particularly to a redistributed chip packaging for an integrated circuit. The integrated circuit package includes an integrated circuit having a protective material on at least a portion of the integrated circuit. A lead frame is coupled to the integrated circuit and a conductive layer is also coupled to the interconnect. A solder ball is coupled to the conductive layer and a passivation layer is on the conductive layer. Active and passive components are electrically coupled to the integrated circuit.

Claims (53)

1. A method of forming an integrated circuit package comprising:

forming a lead frame comprising a first portion and a second portion, wherein the first portion and the second portion intersect at an angle ranging from 45 degrees to 135 degrees;

forming an adhesive material on the first portion of the lead frame;

attaching a carrier to the lead frame with the adhesive material;

attaching an integrated circuit to the adhesive material;

forming an interconnect on the integrated circuit;

forming a protective material on the integrated circuit;

removing the carrier and the adhesive material;

removing a portion of the protective material to expose the interconnect and the second portion of the lead frame; and

removing the first portion of the lead frame.

2. The method of claim 1 , wherein the angle is in the range from 85 degrees to 95 degrees.

3. The method of claim 1 , wherein forming the protective layer comprises heating an epoxy material to a temperature in the range from 120° C. to 150° C. to harden the epoxy material.

4. The method of claim 3 , wherein removing the carrier and the adhesive material comprises heating the epoxy material to a temperature from 175° C. to 260° C. to thermally release the adhesive material and carrier.

5. The method of claim 1 , wherein removing the portion of the protective material comprises grinding an upper surface thereof.

6. The method of claim 1 , further comprising:

forming a conductive material on the protective layer;

forming a passivation layer on the conductive material; and

forming a solder ball on the passivation layer, wherein the solder ball is electrically coupled to the conductive material.

7. A method of making an integrated circuit package comprising:

forming a lead frame comprising a first portion and a second portion, wherein the first portion and the second portion intersect at an angle ranging from 45 degrees to 135 degrees;

adhering a double-sided thermal tape to a bottom surface of the first portion of the lead frame;

attaching a carrier to the lead frame with the double-sided thermal tape;

attaching an integrated circuit to the double-sided thermal tape adjacent to the first portion of the lead frame;

forming at least one pillar interconnect on the integrated circuit;

forming a compressive compound over the integrated circuit and the first and second portions of the lead frame;

hardening the compressive compound by heating the compressive compound to a temperature in the range from 120° C. to 150° C.;

removing a portion of the compressive compound to expose the at least one pillar interconnect and the second portion of the lead frame; and

removing the first portion of the lead frame.

8. The method of claim 7 , wherein the removing the portion of compressive compound comprises grinding an upper surface thereof.

9. The method of claim 8 , further comprising:

forming a conductive material on the compressive compound;

forming a first passivation layer on an upper surface of the conductive material;

forming a second passivation layer on a lower surface of the compressive compound; and

forming a solder ball on the first passivation layer, wherein the solder ball is electrically coupled to the conductive material.

10. The method of claim 7 , wherein the compressive compound comprises an epoxy material.

11. The method of claim 7 , further comprising attaching a component to the lower surface of the compressive compound.

12. A method of forming an integrated circuit package comprising:

forming a lead frame comprising a first portion and a second portion transverse to the first portion;

forming an adhesive material on the first portion of the lead frame;

attaching a carrier to the lead frame with the adhesive material;

attaching an integrated circuit to the adhesive material;

forming an interconnect on the integrated circuit;

forming a protective material on the integrated circuit;

removing the carrier and the adhesive material;

removing a portion of the protective material to expose the interconnect and the second portion of the lead frame; and

removing the first portion of the lead frame.

13. The method of claim 12 , wherein forming the protective material comprises heating an epoxy material to a temperature in the range from 120° C. to 150° C. to harden the epoxy material.

14. The method of claim 13 , wherein removing the carrier and the adhesive material comprises heating the epoxy material to a temperature from 175° C. to 260° C. to thermally release the adhesive material and carrier.

15. The method of claim 12 , wherein removing the portion of the protective material comprises grinding an upper surface thereof.

16. The method of claim 12 further comprising:

forming a conductive material on the protective material;

forming a passivation layer on the conductive material; and

forming a solder ball on the passivation layer, wherein the solder ball is electrically coupled to the conductive material.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2024
From: STMICROELECTRONICS PTE LTD
To: STMICROELECTRONICS INTERNATIONAL N.V.
Reel/Frame 068433/0985 →
Continuity (3)
Division 12578382 · Oct 13, 2009
Provisional Application 61147430 · Jan 26, 2009
Related Publication 20150303168A1 · Oct 22, 2015