Synthesis of reduced netlist having positive elements and no controlled sources
In one embodiment, a circuit analysis method includes obtaining a netlist of a circuit, generating a reduced model from the netlist, using the reduced model to synthesize a positive netlist having no controlled current or voltage sources, unstamping the synthesized positive netlist, and simulating the circuit using the unstamped synthesized positive netlist.
1. A circuit analysis method comprising:
obtaining a netlist of a circuit;
generating a reduced model from the netlist;
using a processor to synthesize from the reduced model a positive netlist having no controlled current or voltage sources; and
unstamping the synthesized positive netlist,
wherein generating a reduced model from the netlist includes performing Tichonov regularization.
2. The method of claim 1 , wherein the reduced model is representable as a second-order formulation given as
(
s
Q
~
+
N
~
+
F
~
s
)
x
~
=
A
i
u
where
A
i
=
(
I
K
×
K
0
(
q
-
K
)
×
K
)
{tilde over (Q)}: Reduced capacitance matrix
Ñ: Reduced resistor matrix
{tilde over (F)}: Reduced susceptance (inverse of inductance) matrix
{tilde over (x)}: Reduced state-space vector including the node voltages and the branch currents for inductors
u: Input vector including the voltage sources applied in the ports
s: Laplace frequency notation
K: Number of ports
q: Number of nodes in the reduced netlist
and wherein using the reduced model to synthesize a positive netlist comprises:
introducing into the second-order formulation k virtual susceptances, where k is a number of circuit terminals, to achieve the formulation
(
s
(
0
k
×
k
0
k
×
q
0
q
×
k
Q
~
)
+
(
0
k
×
k
0
k
×
q
0
q
×
k
N
~
)
+
1
s
(
F
1
F
2
F
2
T
F
~
)
)
x
~
=
(
I
K
×
K
0
q
×
K
)
u
applying positive definite enforcement (PDE)
performing a first singular value decomposition on the matrix {tilde over (Q)}, represented as {tilde over (Q)}=X Q S Q X Q T , to achieve
(
s
(
0
0
0
X
Q
S
Q
X
Q
T
)
+
(
0
0
0
N
~
)
+
1
s
(
F
1
F
2
F
2
T
F
~
)
)
x
~
=
(
I
0
)
u
considering the matrix T Q =X Q S Q −1/2 , applying a first transformation
(
(
I
0
0
T
Q
T
)
(
s
(
0
0
0
X
Q
S
Q
X
Q
T
)
+
(
0
0
0
N
~
)
+
1
s
(
F
1
F
2
F
2
T
F
~
)
)
(
I
0
0
T
Q
)
)
x
~
=
(
I
0
0
T
Q
)
(
I
0
)
u
to achieve to the identity matrix I
(
s
(
0
0
0
1
)
+
(
0
0
0
T
Q
T
N
~
T
Q
)
+
1
s
(
F
1
F
2
T
Q
T
Q
T
F
2
T
T
Q
T
F
~
T
Q
)
)
x
~
=
(
I
0
)
u
performing a second singular value decomposition to T Q T ÑT Q =X N S N X N T to achieve
(
s
(
0
0
0
1
)
+
(
0
0
0
X
N
S
N
X
N
T
)
+
1
s
(
F
1
F
2
T
Q
T
Q
T
F
2
T
T
Q
T
F
~
T
Q
)
)
x
~
=
(
I
0
)
u
applying a second transformation,
(
(
I
0
0
X
N
T
)
(
s
(
0
0
0
I
)
+
(
0
0
0
X
N
S
N
X
N
T
)
+
1
s
(
F
1
F
2
T
Q
T
Q
T
F
2
T
T
Q
T
F
~
T
Q
)
)
(
I
0
0
X
N
)
)
x
~
=
(
I
0
0
X
N
T
)
(
I
0
)
u
to obtain
(
s
(
0
0
0
I
)
+
(
0
0
0
S
N
)
+
1
s
(
F
1
F
2
T
Q
X
N
X
N
T
T
Q
T
F
2
T
X
N
T
T
Q
T
F
~
T
Q
X
N
)
)
x
~
=
(
I
0
)
u
considering the following matrices
F′ 2 =F 2 T Q X N
F 3 =X N T T Q T {tilde over (F)}T Q X N
representing the circuit as
(
s
(
0
0
0
I
)
+
(
0
0
0
S
N
)
+
1
s
(
F
1
F
2
′
F
2
′
T
F
3
)
)
x
~
=
(
I
0
)
u
3. The method of claim 2 , wherein the identity matrix I and the positive valued diagonal matrix S N correspond respectively to the reduced capacitor {tilde over (Q)} and resistor Ñ matrices, and wherein the unstamping is a direct unstamping of the identity matrix I and the positive valued diagonal matrix S N by constant value capacitors to Gnd and positive resistors respectively.
4. The method of claim 2 , further comprising inverting and unstamping susceptance matrix
F
~
=
(
F
1
F
2
′
F
2
′
T
F
3
)
using inductors and mutual inductance (k) elements.
5. The method of claim 4 , wherein the susceptance matrix
F
~
=
(
F
1
F
2
′
F
2
′
T
F
3
)
is enforced to positive definite, the inverse inductance matrix is positive definite, diagonal elements of the inverse inductance matrix are positive and are synthesized with positive inductances to ground, and non-diagonal elements of the inverse inductance matrix are synthesized as k-elements between each pair of indices of non-diagonal elements.
6. The method of claim 1 , further comprising:
generating a DC behavior extraction model, and
merging the DC behavior extraction model with the synthesized a positive netlist.
7. The method of 6 , wherein the generating the DC behavior extraction model includes:
formulating a Z parameter matrix of the reduced positive netlist, given by
Z
=
(
A
i
0
)
T
(
(
N
~
E
~
l
-
E
~
l
T
0
)
+
s
(
Q
~
0
0
F
~
)
)
-
1
(
A
i
0
)
calculating the Z matrix at DC,
evaluating the Y matrix, with Y=Z −1 .
8. The method of claim 7 , further comprising unstamping the Y matrix as follows:
A resistor R ij =−1/Y ij is inserted between ports i, j
A resistor R i =1/(Σ j=1 m K ij ) is inserted between port i and gnd.
9. The method of claim 1 , further comprising performing modified nodal analysis (MNA) using the formulations
C
x
.
+
Gx
=
Bu
y
=
B
T
x
wherein
x
=
[
v
n
i
l
i
v
]
u
=
[
-
i
v
v
]
y
=
[
v
i
i
v
]
C
=
[
Q
0
0
l
]
G
=
[
N
A
l
T
-
A
l
0
]
B
=
[
A
i
0
]
Q
=
A
c
T
cA
c
,
N
=
A
g
T
g
A
g
Where
:
B
∈
R
(
N
V
+
N
l
+
K
)
×
K
,
A
i
∈
R
K
×
K
,
N
∈
R
(
N
V
+
K
)
×
(
N
V
+
K
)
,
Q
∈
R
(
N
V
+
K
)
×
(
N
V
+
K
)
,
l
∈
R
N
l
×
N
l
,
A
l
T
∈
R
(
N
V
+
K
)
×
N
l
and Nv is the number of internal nodes, N l is the number of inductors and K the number of ports,
and storing only Q, l, N, A l sub-matrices instead of the dense matrices C and G.
10. The method of claim 1 , further comprising simulating the circuit using the unstamped synthesized positive netlist.
11. A circuit analysis system comprising:
a memory;
a processor for executing instructions stored in the memory, the instructions implementing:
a reduced model generator operable to generate a reduced model of a circuit from a netlist of the circuit, wherein generating a reduced model from the netlist includes performing Tichonov regularization; and
a positive netlist synthesizer operable to generate a positive netlist from the reduced model, the positive netlist having no controlled current or voltage sources.
12. The system of claim 11 , wherein the reduced model is representable as a second-order formulation given as
(
s
Q
~
+
N
~
+
F
~
s
)
x
~
=
A
i
u
where
A
i
=
(
I
K
×
K
0
(
q
-
K
)
×
K
)
and
{tilde over (Q)}: Reduced capacitance matrix
Ñ: Reduced resistor matrix
{tilde over (F)}: Reduced susceptance (inverse of inductance) matrix
{tilde over (x)}: Reduced state-space vector including the node voltages and the branch currents for inductors
u: Input vector including the voltage sources applied in the ports
s: Laplace frequency notation
K: Number of ports
q: Number of nodes in the reduced netlist
and wherein the positive netlist synthesizer is further operable to:
introduce into the second-order formulation k virtual susceptances, where k is a number of circuit terminals, to achieve the formulation
(
s
(
0
k
×
k
0
k
×
q
0
q
×
k
Q
~
)
+
(
0
k
×
k
0
k
×
q
0
q
×
k
N
~
)
+
1
s
(
F
1
F
2
F
2
T
F
~
)
)
x
~
=
(
I
K
×
K
0
q
×
K
)
u
apply positive definite enforcement (PDE)
perform a first singular value decomposition on the matrix {tilde over (Q)}, represented as {tilde over (Q)}=X Q S Q X Q T , to achieve
(
s
(
0
0
0
X
Q
S
Q
X
Q
T
)
+
(
0
0
0
N
~
)
+
1
s
(
F
1
F
2
F
2
T
F
~
)
)
x
~
=
(
I
0
)
u
considering the matrix T Q =X Q S Q −1/2 , applying a first transformation
(
(
I
0
0
T
Q
T
)
(
s
(
0
0
0
X
Q
S
Q
X
Q
T
)
+
(
0
0
0
N
~
)
+
1
s
(
F
1
F
2
F
2
T
F
~
)
)
(
I
0
0
T
Q
)
)
x
~
=
(
I
0
0
T
Q
T
)
(
I
0
)
u
to achieve to the identity matrix I
(
s
(
0
0
0
I
)
+
(
0
0
0
T
Q
T
N
~
T
Q
)
+
1
s
(
F
1
F
2
T
Q
T
Q
T
F
2
T
T
Q
T
F
~
T
Q
)
)
x
~
=
(
I
0
)
u
perform a second singular value decomposition to T Q T ÑT Q =X N S N X N T to achieve
(
s
(
0
0
0
I
)
+
(
0
0
0
X
N
S
N
X
N
T
)
+
1
s
(
F
1
F
2
T
Q
T
Q
T
F
2
T
T
Q
T
F
~
T
Q
)
)
x
~
=
(
I
0
)
u
apply a second transformation,
(
(
I
0
0
X
N
T
)
(
s
(
0
0
0
I
)
+
(
0
0
0
X
N
S
N
X
N
T
)
+
1
s
(
F
1
F
2
T
Q
T
Q
T
F
2
T
T
Q
T
F
~
T
Q
)
)
(
I
0
0
X
N
)
)
x
~
=
(
I
0
0
X
N
T
)
(
I
0
)
u
to obtain
(
s
(
0
0
0
I
)
+
(
0
0
0
S
N
)
+
1
s
(
F
1
F
2
T
Q
X
N
X
N
T
T
Q
T
F
2
T
X
N
T
T
Q
T
F
~
T
Q
X
N
)
)
x
~
=
(
I
0
)
u
considering the following matrices
F′ 2 =F 2 T Q X N
F 3 =X N T T Q T {tilde over (F)}T Q X N
represent the circuit as
(
s
(
0
0
0
I
)
+
(
0
0
0
S
N
)
+
1
s
(
F
1
F
2
′
F
2
′
T
F
3
)
)
x
~
=
(
I
0
)
u
13. The system of claim 12 , wherein the identity matrix I and the positive valued diagonal matrix S N correspond respectively to the reduced capacitor {tilde over (Q)} and resistor Ñ matrices.
14. The system of claim 11 , further comprising:
a DC behavior extractor for generating a model of the DC behavior of the circuit; and
a merger for merging the a positive netlist and the model of the DC behavior.
15. The system of 14 , wherein generating the DC behavior extraction model includes:
formulating a Z parameter matrix of the reduced positive netlist, given by
Z
=
(
A
i
0
)
T
(
(
N
~
E
~
l
-
E
~
l
T
0
)
+
s
(
Q
~
0
0
F
~
)
)
-
1
(
A
i
0
)
calculating the Z matrix at DC,
evaluating the Y matrix, with Y=Z −1 .
16. The system of claim 11 , further comprising a circuit analyzer for analyzing the circuit based on the positive netlist.
17. A non-transitory program storage device readable by a machine, embodying a program of instructions executable by the machine to perform a circuit analysis method, the method comprising:
obtaining a netlist of a circuit;
generating a reduced model from the netlist, wherein generating a reduced model from the netlist includes performing Tichonov regularization;
using the reduced model to synthesize a positive netlist having no controlled current or voltage sources; and
unstamping the synthesized positive netlist.
18. The device of claim 17 , wherein the reduced model is representable as a second-order formulation given as
(
s
Q
~
+
N
~
+
F
~
s
)
x
~
=
A
i
u
where
A
i
=
(
I
K
×
K
0
(
q
-
K
)
×
K
)
and
{tilde over (Q)}: Reduced capacitance matrix
Ñ: Reduced resistor matrix
{tilde over (F)}: Reduced susceptance (inverse of inductance) matrix
{tilde over (x)}: Reduced state-space vector including the node voltages and the branch currents for inductors
u: Input vector including the voltage sources applied in the ports
s: Laplace frequency notation
K: Number of ports
q: Number of nodes in the reduced netlist
and wherein using the reduced model to synthesize a positive netlist comprises:
introducing into the second-order formulation k virtual susceptances, where k is a number of circuit terminals, to achieve the formulation
(
s
(
0
k
×
k
0
k
×
q
0
q
×
k
Q
~
)
+
(
0
k
×
k
0
k
×
q
0
q
×
k
N
~
)
+
1
s
(
F
1
F
2
F
2
T
F
~
)
)
=
x
~
(
I
K
×
K
0
q
×
K
)
u
applying positive definite enforcement (PDE)
performing a first singular value decomposition on the matrix {tilde over (Q)}, represented as {tilde over (Q)}=X Q S Q X Q T , to achieve
(
s
(
0
0
0
X
Q
S
Q
X
Q
T
)
+
(
0
0
0
N
~
)
+
1
s
(
F
1
F
2
F
2
T
F
~
)
)
x
~
=
(
I
0
)
u
considering the matrix T Q =X Q S Q −1/2 , applying a first transformation
(
(
I
0
0
T
Q
T
)
(
s
(
0
0
0
X
Q
S
Q
X
Q
T
)
+
(
0
0
0
N
~
)
+
1
s
(
F
1
F
2
F
2
T
F
~
)
)
(
I
0
0
T
Q
)
)
x
~
=
(
I
0
0
T
Q
T
)
(
I
0
)
u
to achieve to the identity matrix I
(
s
(
0
0
0
I
)
+
(
0
0
0
T
Q
T
N
~
T
Q
)
+
1
s
(
F
1
F
2
T
Q
T
Q
T
F
2
T
T
Q
T
F
~
T
Q
)
)
x
~
=
(
I
0
)
u
performing a second singular value decomposition to T Q T ÑT Q =X N S N X N T to achieve
(
s
(
0
0
0
I
)
+
(
0
0
0
X
N
S
N
X
N
T
)
+
1
s
(
F
1
F
2
T
Q
T
Q
T
F
2
T
T
Q
T
F
~
T
Q
)
)
x
~
=
(
I
0
)
u
applying a second transformation,
(
(
I
0
0
X
N
T
)
(
s
(
0
0
0
I
)
+
(
0
0
0
X
N
S
N
X
N
T
)
+
1
s
(
F
1
F
2
T
Q
T
Q
T
F
2
T
T
Q
T
F
~
T
Q
)
)
(
I
0
0
X
N
)
)
x
~
=
(
I
0
0
X
N
T
)
(
I
0
)
u
to obtain
(
s
(
0
0
0
I
)
+
(
0
0
0
S
N
)
+
1
s
(
F
1
F
2
T
Q
X
N
X
N
T
T
Q
T
F
2
T
X
N
T
T
Q
T
F
~
T
Q
X
N
)
)
x
~
=
(
I
0
)
u
considering the following matrices
F′ 2 =F 2 T Q X N
F 3 =X N T T Q T {tilde over (F)}T Q X N
representing the circuit as
(
s
(
0
0
0
I
)
+
(
0
0
0
S
N
)
+
1
s
(
F
1
F
2
′
F
2
′
T
F
3
)
)
x
~
=
(
I
0
)
u
19. The device of claim 18 , wherein the identity matrix I and the positive valued diagonal matrix S N correspond respectively to the reduced capacitor {tilde over (Q)} and resistor Ñ matrices, and wherein the unstamping is a direct unstamping of the identity matrix I and the positive valued diagonal matrix S N by constant value capacitors to Gnd and positive resistors respectively.
20. The device of claim 18 , the method further comprising inverting and unstamping susceptance matrix
F
~
=
(
F
1
F
2
′
F
2
′
T
F
3
)
using inductors and mutial inductance (k) elements.
21. The device of claim 20 , wherein the susceptance matrix
F
~
=
(
F
1
F
2
′
F
2
′
T
F
3
)
is enforced to positive definite, the inverse inductance matrix is positive definite, diagonal elements of the inverse inductance matrix are positive and are synthesized with positive inductances to ground, and non-diagonal elements of the inverse inductance matrix are synthesized as k-elements between each pair of indices of non-diagonal elements.
22. The device of claim 17 , the method further comprising:
generating a DC behavior extraction model, and
merging the DC behavior extraction model with the synthesized a positive netlist.
23. The device of 22 , wherein the generating the DC behavior extraction model includes:
formulating a Z parameter matrix of the reduced positive netlist, given by
Z
=
(
A
i
0
)
T
(
(
N
~
E
~
l
-
E
~
l
T
0
)
+
s
(
Q
~
0
0
F
~
)
)
-
1
(
A
i
0
)
calculating the Z matrix at DC,
evaluating the Y matrix, with Y=Z −1 .
24. The device of claim 23 , the method further comprising unstamping the Y matrix as follows:
A resistor R ij =−1/Y ij is inserted between ports i, j
A resistor R i =1/(Σ j=1 m Y ij ) is inserted between port i and gnd.
25. The device of claim 17 , the method further comprising performing modified nodal analysis (MNA) using the formulations
C
x
.
+
Gx
=
Bu
y
=
B
T
x
wherein
x
=
[
v
n
i
l
i
v
]
u
=
[
-
i
i
v
v
]
y
=
[
v
i
i
v
]
C
=
[
Q
0
0
l
]
G
=
[
N
A
l
T
-
A
l
0
]
B
=
[
A
i
0
]
Q
=
A
c
T
cA
c
,
N
=
A
g
T
gA
g
Where
:
B
∈
R
(
N
V
+
N
l
+
K
)
×
K
,
A
i
∈
R
K
×
K
,
N
∈
R
(
N
V
+
K
)
×
(
N
V
+
K
)
,
Q
∈
R
(
N
V
+
K
)
×
(
N
V
+
K
)
,
l
∈
R
N
l
×
N
l
,
A
l
T
∈
R
(
N
V
+
K
)
×
N
l
and Nv is the number of internal nodes, N l is the number of inductors and K the number of ports,
and storing only Q, l, N, A l sub-matrices instead of the dense matrices C and G.
26. The device of claim 17 , the method further comprising simulating the circuit using the unstamped synthesized positive netlist.