Synthesis of DC accurate noise compatible reduced netlist
In one embodiment, a circuit analysis method includes obtaining a netlist of a circuit, generating a reduced model from the netlist, using the reduced model to synthesize a noise compatible netlist, ensuring accurate DC behavior, and simulating the circuit using the synthesized netlist.
1. A circuit analysis method comprising:
obtaining a netlist of a circuit;
generating a reduced model from the netlist;
using the reduced model to synthesize a DC-accurate noise compatible netlist utilizing positive resistors and inductors, negative capacitors and ideal transformers, said synthesizing including applying susceptance filtering based on an initial threshold value and applying DC error control;
analyzing the circuit using the synthesized DC-accurate noise compatible netlist; and
fabricating the circuit using the results of the analysis.
2. The method of claim 1 , wherein generating a reduced model from the netlist includes performing Tichonov regularization.
3. The method of claim 1 , wherein the reduced model is representable as a second-order formulation given as
(
s
Q
~
+
N
~
+
F
~
s
)
x
~
=
A
i
u
where
A
i
=
(
I
KxK
0
(
q
-
K
)
xK
)
and
{tilde over (Q)}: Reduced capacitance matrix
Ñ: Reduced resistor matrix
{tilde over (F)}: Reduced susceptance (inverse of inductance) matrix
{tilde over (x)}: Reduced state-space vector including the node voltages and the branch currents for inductors
u: Input vector including the voltage sources applied in the ports
s: Laplace frequency notation
K: Number of ports
q: Number of nodes in the reduced netlist
and wherein using the reduced model to synthesize a positive netlist comprises:
applying positive definite enforcement (PDE)
performing a first singular value decomposition on the matrix Ñ, represented as
Ñ=X N S N X N T ,
to achieve
(
s
Q
~
+
X
N
S
N
X
N
T
+
F
~
s
)
x
~
=
A
i
u
considering the matrix T N =X N S N −1/2 , applying a first transformation
T
N
T
(
s
Q
~
+
X
N
S
N
X
N
T
+
F
~
s
)
T
N
x
~
=
T
N
T
A
i
u
to achieve to the identity matrix I
(
sT
N
T
Q
~
T
N
+
I
+
T
N
T
F
~
T
N
s
)
x
~
=
T
N
T
A
i
u
performing a second singular value decomposition T N T {tilde over (F)}T N =T F S F T F T to achieve
(
sT
N
T
Q
~
T
N
+
I
+
T
F
S
F
T
F
T
s
)
x
~
=
T
N
T
A
i
u
applying a second transformation,
T
F
T
(
sT
N
T
Q
~
T
N
+
I
+
T
F
S
F
T
F
T
s
)
T
F
x
~
=
T
F
T
T
N
T
A
i
u
to obtain
(
sT
F
T
T
N
T
Q
~
T
N
T
F
+
I
+
S
F
s
)
x
~
=
T
F
T
T
N
T
A
i
u
considering the following matrices
Q new =T F T T N T {tilde over (Q)}T N T F
A i,new =T F T T N T A i ,
representing the circuit as
(
sQ
new
+
I
+
S
F
s
)
x
~
=
A
i
,
new
u
4. The method of claim 3 , wherein the identity matrix I and the positive valued diagonal matrix S F correspond respectively to the reduced resistor Ñ and susceptance {tilde over (F)} matrices, the method further including direct unstamping of the identity matrix I and the positive valued diagonal matrix S F by constant value positive resistors and positive inductors to Gnd respectively.
5. The method of claim 3 , further comprising extracting DC behavior of the netlist by introducing a dynamic susceptance filtering scheme.
6. The method of claim 5 , wherein the DC extraction includes:
applying a first susceptance filtering based on an initial threshold value
calculating DC error control of the netlist with respect to the reduced matrices, based on the following relation:
max
i
=
1
…
N
(
S
~
netlist
(
D
C
)
-
S
~
system
(
D
C
)
S
~
system
(
D
C
)
)
where {tilde over (S)} netlist(DC) and {tilde over (S)} system(DC) is the S function of the reduced netlist and reduced matrix description of the system respectively, calculated at DC,
increasing the initial threshold value if a calculated error value is above a predefined value
synthesizing a DC accurate netlist when the calculated error value becomes lower than a predefined value.
7. The method of claim 5 , further comprising replacing controlled sources with ideal transformers.
8. A non-transitory program storage device readable by a machine, embodying a program of instructions executable by the machine to perform a circuit analysis method, the method comprising:
obtaining a netlist of a circuit;
generating a reduced model from the netlist; and
using the reduced model to synthesize a DC-accurate noise compatible netlist utilizing positive resistors and inductors, negative capacitors and ideal transformers, said synthesizing including applying susceptance filtering based on an initial threshold value and applying DC error control;
analyzing the circuit using the synthesized DC-accurate noise compatible netlist; and
fabricating the circuit using the results of the analysis.
9. The device of claim 8 , wherein generating a reduced model from the netlist includes performing Tichonov regularization.
10. The device of claim 8 , wherein the reduced model is representable as a second-order formulation given as
(
s
Q
~
+
N
~
+
F
~
s
)
x
~
=
A
i
u
where
A
i
=
(
I
Kx
K
0
(
q
-
K
)
x
K
)
and
{tilde over (Q)}: Reduced capacitance matrix
Ñ: Reduced resistor matrix
{tilde over (F)}: Reduced susceptance (inverse of inductance) matrix
{tilde over (x)}: Reduced state-space vector including the node voltages and the branch currents for inductors
u: Input vector including the voltage sources applied in the ports
s: Laplace frequency notation
K: Number of ports
q: Number of nodes in the reduced netlist
and wherein using the reduced model to synthesize a positive netlist comprises:
applying positive definite enforcement (PDE)
performing a first singular value decomposition on the matrix Ñ, represented as
Ñ=X N S N X N T ,
to achieve
(
s
Q
~
+
X
N
S
N
X
N
T
+
F
~
s
)
x
~
=
A
i
u
considering the matrix T N =X N S N −1/2 , applying a first transformation
T
N
T
(
s
Q
~
+
X
N
S
N
X
N
T
+
F
~
s
)
T
N
x
~
=
T
N
T
A
i
u
to achieve to the identity matrix I
(
sT
N
T
Q
~
T
N
+
I
+
T
N
T
F
~
T
N
s
)
x
~
=
T
N
T
A
i
u
performing a second singular value decomposition T N T {acute over (F)}T N =T F S F T F T to achieve
(
sT
N
T
Q
~
T
N
+
I
+
T
F
S
F
T
F
T
s
)
x
~
=
T
N
T
A
i
u
applying a second transformation,
T
F
T
(
sT
N
T
Q
~
T
N
+
I
+
T
F
S
F
T
F
T
s
)
T
F
x
~
=
T
F
T
T
N
T
A
i
u
to obtain
(
sT
F
T
T
N
T
Q
~
T
N
T
F
+
I
+
S
F
s
)
x
~
=
T
F
T
T
N
T
A
i
u
considering the following matrices
Q new =T F T T N T {tilde over (Q)}T N T F
A i,new =T F T T N T A i ,
representing the circuit as
(
sQ
new
+
I
+
S
F
s
)
x
~
=
A
i
,
new
u
11. The device of claim 10 , wherein the identity matrix I and the positive valued diagonal matrix S F correspond respectively to the reduced resistor Ñ and susceptance {tilde over (F)} matrices, the method further including direct unstamping of the identity matrix I and the positive valued diagonal matrix S F by constant value positive resistors and positive inductors to Gnd respectively.
12. The device of claim 10 , the method further comprising extracting DC behavior of the netlist by introducing a dynamic susceptance filtering scheme.
13. The device of claim 12 , wherein the DC extraction includes:
applying a first susceptance filtering based on an initial threshold value
calculating DC error control of the netlist with respect to the reduced matrices, based on the following relation:
max
i
=
1
…
N
(
S
~
netlist
(
D
C
)
-
S
~
system
(
D
C
)
S
~
system
(
D
C
)
)
where {tilde over (S)} netlist(DC) and {tilde over (S)} system(DC) is the S function of the reduced netlist and reduced matrix description of the system respectively, calculated at DC,
increasing the initial threshold value if a calculated error value is above a predefined value
synthesizing a DC accurate netlist when the calculated error value becomes lower than a predefined value.
14. The device of claim 12 , further comprising replacing controlled sources with ideal transformers.