IP Library Granted Patent US 10,356,902
Granted Patent B2
US 10,356,902 · App. 14/757,984 · Granted Jul 16, 2019

Board to board interconnect

Inventors: Chee Ling Wong (Sungai Ara, MY); Wil Choon Song (Bayan Lepas, MY); Khang Choong Yong (Puchong, MY); Eng Huat Goh (Ayer Itam, MY); Mohd Muhaiyiddin Bin Abdullah (Kepala Batas, MY); Tin Poay Chuah (Bayan Lepas, MY)
Assignee: Intel Corporation
H05K1/117H05K1/142H05K1/0298H05K2201/09845
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Quick Facts
Patent No.
US 10,356,902
App. No.
14/757,984
Granted
Jul 16, 2019
Kind
B2
Abstract

A system for board-to-board interconnect is described herein. The system includes a first printed circuit board (PCB) having a first recess along a first edge of the first PCB that exposes a first solder pad on a layer of the first PCB. The system also includes a second PCB having a second recess along a second edge of the second PCB that exposes a second solder pad on a layer of the second PCB. The second recess is complementary to the first recess to allow the first PCB to mate with the second PCB. The first solder pad is aligned with the second solder pad when the first PCB is mated with the second PCB. The system additionally includes an assembly configured to electronically couple the first solder pad with the second solder pad.

Claims (21)

1. A system, comprising:

a first printed circuit board (PCB) having a first recess along a first edge of the first PCB, wherein the first recess includes a first plurality of alternating blocks, the first plurality of alternating blocks including a first set of blocks that expose a first solder pad on a first layer of the first PCB and a second set of blocks that expose a second solder pad on a second layer of the first PCB;

a second PCB having a second recess along a second edge of the second PCB, wherein the second recess is complementary to the first recess and exposes a solder pad on a layer of the second PCB;

wherein:

the first solder pad is electrically coupled to the solder pad on the layer of the second PCB by at least a metallized particle interconnect, with the first solder pad aligned with the solder pad on the layer of the second PCB;

the first and second PCB are physically coupled together to form a removable assembly by a removable clamping mechanism; and

a z-height of the first PCB, a z-height of the second PCB and a z-height of the first PCB and the second PCB when physically coupled are substantially equal.

2. The system of claim 1 , wherein the first PCB is a system in package (SIP) and the second PCB is an IO board.

3. The system of claim 2 , wherein the IO board includes a cavity to house the first PCB.

4. The system of claim 1 , wherein the metallized particle interconnect includes a conductive material comprising an elastomer.

5. The system of claim 1 , wherein the second recess comprises a second plurality of alternating blocks that are complementary to the first plurality of alternating blocks.

6. A method for interconnecting a first printed circuit board (PCB) and a second PCB, comprising:

generating a first recess along a first edge of the first PCB, the first recess comprising a first plurality of alternating blocks, the first plurality of alternating blocks including a first set of blocks that expose a first solder pad on a first layer of the first PCB and a second set of blocks that expose a second solder pad on a second layer of the first PCB;

generating a second recess along a second edge of the second PCB, wherein the second recess is complementary to the first recess and exposes a solder pad on a layer of the second PCB;

electrically connecting the first solder pad and the solder pad on the layer of the second PCB with a conductive material including at least a metallized particle interconnect; and

physically coupling the first edge of the first PCB to the second edge of the second PCB with a removable clamping mechanism to form a removable assembly;

wherein a z-height of the first PCB, a z-height of the second PCB and a z-height of the first PCB and the second PCB when physically coupled are substantially equal.

7. The method of claim 6 , wherein the first PCB is a SIP and the second PCB is an IO board.

8. The method of claim 7 , wherein the IO board includes a cavity to house the SIP.

9. The method of claim 6 , wherein the metallized particle interconnect further comprises conductive material comprising an elastomer.

10. The method of claim 8 , wherein generating the second recess comprises generating a second plurality of alternating blocks on the second PCB that are complementary to the first plurality of alternating blocks.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 3, 2016
From: WONG, CHEE LING; SONG, WIL CHOON; YONG, KHANG CHOONG; GOH, ENG HUAT; BIN ABDULLAH, MOHD MUHAIYIDDIN; CHUAH, TIN POAY
To: INTEL CORPORATION
Reel/Frame 037878/0873 →
Continuity (1)
Related Publication 20170188461A1 · Jun 29, 2017