Multilayer passivation or etch stop TFT
The present invention generally relates to TFTs and methods for fabricating TFTs. For either back channel etch TFTs or for etch stop TFTs, multiple layers for the passivation layer or the etch stop layers permits a very dense capping layer to be formed over a less dense back channel protection layer. The capping layer can be sufficiently dense so that few pin holes are present and thus, hydrogen may not pass through to the semiconductor layer. As such, hydrogen containing precursors may be used for the capping layer deposition.
1. A thin film transistor, comprising:
a substrate having a gate electrode, a gate dielectric layer and a semiconductor layer formed thereover;
a source electrode completely disposed over the semiconductor layer;
a drain electrode completely disposed over the semiconductor layer and spaced from the source electrode by an active channel that comprises an exposed portion of the semiconductor layer;
a back channel protection layer disposed on the exposed portion of the semiconductor layer in the active channel; and
an etch stop layer disposed on the back channel protection layer, the etch stop layer having a different composition than the back channel protection layer.
2. The thin film transistor of claim 1 , wherein the etch stop layer has a greater thickness than the back channel protection layer.
3. The thin film transistor of claim 1 , wherein the etch stop layer is more dense than the back channel protection layer.
4. The thin film transistor of claim 1 , wherein both the back channel protection layer and the etch stop layer comprise SiOx.
5. The thin film transistor of claim 1 , wherein the etch stop layer has a thickness of greater than 500 Angstroms.
6. The thin film transistor of claim 1 , wherein the semiconductor layer comprises IGZO or ZnON.
7. A method of making a thin film transistor, comprising:
depositing a back channel protection layer over a semiconductor layer using a first set of processing conditions, the semiconductor layer is disposed over a gate dielectric layer, a gate electrode and a substrate;
depositing an etch stop layer over the back channel protection layer using a second set of process conditions different than the first set of process conditions, wherein a substrate temperature during deposition of the etch stop layer is less than 250 Celsius; and
forming source and drain electrodes completely over the semiconductor layer and adjacent both the back channel protection layer and the etch stop layer.
8. The method of claim 7 , wherein:
the etch stop layer has a greater thickness than the back channel protection layer; or
the etch stop layer is more dense than the back channel protection layer; or
the etch stop layer is deposited with a N 2 O to silane ratio of greater than about 30; or
the etch stop layer is deposited with a power density of less than 3.34 kW/m 2 and a pressure of less than 1.25 Torr; or
both the back channel protection layer and the etch stop layer comprise SiOx; or
the etch stop layer has a thickness of greater than 500 Angstroms; or
the back channel protection layer and the etch stop layer are deposited by PECVD; or
the back channel protection layer and the etch stop layer are deposited in the same chamber; or
the semiconductor layer comprises IGZO or ZnON.